JPH0211335U - - Google Patents
Info
- Publication number
- JPH0211335U JPH0211335U JP1988088933U JP8893388U JPH0211335U JP H0211335 U JPH0211335 U JP H0211335U JP 1988088933 U JP1988088933 U JP 1988088933U JP 8893388 U JP8893388 U JP 8893388U JP H0211335 U JPH0211335 U JP H0211335U
- Authority
- JP
- Japan
- Prior art keywords
- chip
- integrated circuit
- package
- pads
- thermal conductivity
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/541—Dispositions of bond wires
- H10W72/5449—Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
- H10W72/931—Shapes of bond pads
- H10W72/932—Plan-view shape, i.e. in top view
Landscapes
- Design And Manufacture Of Integrated Circuits (AREA)
Description
第１図はこの考案の一実施例による集積回路装
置の断面図、第２図は第１図真上から見た平面図
、第３図ａ，ｂは従来の集積回路装置を真上から
見た内部を示す平面図および断面図である。図に
おいて、１はパツケージ、２は熱伝導率の良い補
強材、３はチツプ、４はチツプ固定装置、５はす
べり止め、６はパツケージ側パツド、７はチツプ
側パツド、８はピンを示す。なお、図中、同一符
号は同一、又は相当部分を示す。
Figure 1 is a cross-sectional view of an integrated circuit device according to an embodiment of this invention, Figure 2 is a plan view viewed from directly above Figure 1, and Figures 3a and 3b are views of a conventional integrated circuit device viewed from directly above. FIG. 3 is a plan view and a sectional view showing the inside of the device. In the figure, 1 is a package, 2 is a reinforcing material with good thermal conductivity, 3 is a chip, 4 is a chip fixing device, 5 is a non-slip device, 6 is a pad on the package side, 7 is a pad on the chip side, and 8 is a pin. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.
Claims (1)
過程において、パツケージ側のパツドとチツプ側
のパツドを向い合わせ、熱電導性の良い補強材と
固定装置とすべり止めで押しつけ、チツプを着脱
可能になるように実装することを特徴とする集積
回路装置。 In the process of mounting an integrated circuit chip on a package, the pads on the package side and the pads on the chip side are faced and pressed together using reinforcing materials with good thermal conductivity, a fixing device, and a non-slip material, so that the chip can be mounted and removed. An integrated circuit device characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988088933U JPH0211335U (en) | 1988-07-04 | 1988-07-04 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988088933U JPH0211335U (en) | 1988-07-04 | 1988-07-04 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0211335U true JPH0211335U (en) | 1990-01-24 |
Family
ID=31313490
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1988088933U Pending JPH0211335U (en) | 1988-07-04 | 1988-07-04 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0211335U (en) |
-
1988
- 1988-07-04 JP JP1988088933U patent/JPH0211335U/ja active Pending