JPH0211341U - - Google Patents

Info

Publication number
JPH0211341U
JPH0211341U JP1988090779U JP9077988U JPH0211341U JP H0211341 U JPH0211341 U JP H0211341U JP 1988090779 U JP1988090779 U JP 1988090779U JP 9077988 U JP9077988 U JP 9077988U JP H0211341 U JPH0211341 U JP H0211341U
Authority
JP
Japan
Prior art keywords
integrated circuit
insulating film
conductive film
film
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1988090779U
Other languages
English (en)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1988090779U priority Critical patent/JPH0211341U/ja
Publication of JPH0211341U publication Critical patent/JPH0211341U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/536—Shapes of wire connectors the connected ends being ball-shaped

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Description

【図面の簡単な説明】
第1図は本考案の一実施例の縦断面図、第2図
は本考案の他の実施例の縦断面図、第3図は従来
技術の縦断面図である。 1……それ自体で完全に動作する半導体集積回
路、2,22……絶縁膜、3……導電体膜、4…
…封止樹脂、5……ボンデイングワイヤ、6……
電源ライン接続部。

Claims (1)

    【実用新案登録請求の範囲】
  1. 半導体基板表面に形成された集積回路と、該集
    積回路上に設けられた絶縁膜と、前記集積回路の
    外部への接続のための領域以外の前記絶縁膜上に
    設けられ、所定の固定電位が与えられる導電体膜
    と、前記絶縁膜及び前記導電体膜を覆つて設けら
    れた樹脂とを有することを特徴とする半導体集積
    回路。
JP1988090779U 1988-07-07 1988-07-07 Pending JPH0211341U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1988090779U JPH0211341U (ja) 1988-07-07 1988-07-07

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1988090779U JPH0211341U (ja) 1988-07-07 1988-07-07

Publications (1)

Publication Number Publication Date
JPH0211341U true JPH0211341U (ja) 1990-01-24

Family

ID=31315291

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1988090779U Pending JPH0211341U (ja) 1988-07-07 1988-07-07

Country Status (1)

Country Link
JP (1) JPH0211341U (ja)

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