JPH02114931U - - Google Patents
Info
- Publication number
- JPH02114931U JPH02114931U JP1989024503U JP2450389U JPH02114931U JP H02114931 U JPH02114931 U JP H02114931U JP 1989024503 U JP1989024503 U JP 1989024503U JP 2450389 U JP2450389 U JP 2450389U JP H02114931 U JPH02114931 U JP H02114931U
- Authority
- JP
- Japan
- Prior art keywords
- circuit board
- bonding
- pattern
- bonding pattern
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/075—Connecting or disconnecting of bond wires
- H10W72/07551—Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting
- H10W72/07554—Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting changes in dispositions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/541—Dispositions of bond wires
- H10W72/547—Dispositions of multiple bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
- H10W72/931—Shapes of bond pads
- H10W72/932—Plan-view shape, i.e. in top view
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL
Landscapes
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
- Wire Bonding (AREA)
Description
第１図はこの考案の一実施例のボンデイングパ
ターンの要部平面図、第２図は従来例の要部平面
図である。
１Ａ，１Ｂ……第二ボンデイングパターン、１
ａ，１ｂ……第二ボンデイングパターン、２……
ＩＣチツプ、３……第一ボンデイングパターン、
４……回路基板、５……リードワイヤ。
FIG. 1 is a plan view of a main part of a bonding pattern according to an embodiment of this invention, and FIG. 2 is a plan view of a main part of a conventional example. 1A, 1B...second bonding pattern, 1
a, 1b... second bonding pattern, 2...
IC chip, 3...first bonding pattern,
4... Circuit board, 5... Lead wire.
Claims (1)
上の第一ボンデイングパターンと回路基板上の第
二ボンデイングパターンとの間をワイヤボンデイ
ングによつて接続をとる回路基板のボンデイング
パターンにおいて、第二ボンデイングパターンが
第一の端子配設部及び第二の端子配設部に相対応
してそれぞれ千鳥状に配設されるとともに、それ
らの形状が噛合状に形成配置されていることを特
徴としたボンデイングパターン。 In the bonding pattern of the circuit board in which an IC chip is mounted on a circuit board and a first bonding pattern on the IC chip and a second bonding pattern on the circuit board are connected by wire bonding, a second bonding pattern is formed on the circuit board. A bonding device characterized in that the patterns are arranged in a staggered manner in correspondence with each other in the first terminal arrangement part and the second terminal arrangement part, and the shapes thereof are formed and arranged in an interlocking manner. pattern.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1989024503U JPH073637Y2 (en) | 1989-03-03 | 1989-03-03 | Bonding pattern |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1989024503U JPH073637Y2 (en) | 1989-03-03 | 1989-03-03 | Bonding pattern |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02114931U true JPH02114931U (en) | 1990-09-14 |
| JPH073637Y2 JPH073637Y2 (en) | 1995-01-30 |
Family
ID=31244405
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1989024503U Expired - Lifetime JPH073637Y2 (en) | 1989-03-03 | 1989-03-03 | Bonding pattern |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH073637Y2 (en) |
-
1989
- 1989-03-03 JP JP1989024503U patent/JPH073637Y2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH073637Y2 (en) | 1995-01-30 |