JPH0212056B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a bistable multivibrator circuit capable of switching between set and reset states on the rising edge of an input signal supplied to set and reset input terminals, respectively. Another object of the present invention is to provide a bistable multivibrator circuit that can operate stably without being affected by noise components even if a reset input signal contains a large amount of noise components.

Prior Art An example of a conventional bistable multivibrator circuit is shown in FIG. In Fig. 2, 1 is a set input terminal, 2 is a reset input terminal, 3, 4, and 5 are first, second, and third transistors that constitute a current mirror circuit, and 6 is a first transistor that determines the current of the current mirror circuit. The resistor 7 is a fourth transistor whose base and collector are connected to the set input terminal 1 and the first resistor 6, respectively. 8 is a fifth transistor whose collector and base are respectively connected to the collector of the fourth transistor 7 and the collector of the second transistor 4 forming a current mirror. 9 is a sixth transistor whose collector and base are respectively connected to the base of the fifth transistor 8 and the reset input terminal 2; 10 is a third transistor 5 whose collector and base are respectively connected to the output terminal 11 and a current mirror circuit; The 10th connected to the collector of
This is a transistor. 12 is a power supply terminal, 19 is a sixth resistor connected between the base of the fifth transistor 8 and the reference potential, 20 is a seventh resistor connected between the base of the tenth transistor 10 and the reference potential, 23 is a fifth resistor connected to the collector of the tenth transistor 10 and the power supply terminal 12.
In the above configuration, the base-emitter forward voltage V _BE of the fourth transistor 7 is connected to the set input terminal 1.
(hereinafter referred to as V _BE ) or more is input, the fourth transistor 7 becomes conductive, and the first resistor 6 forms the current mirror circuit.
Current flows through the collectors of the second and third transistors 3, 4, and 5. Then, the second transistor 4
When the voltage of the product of the collector current and the sixth resistor 19 exceeds V _BE of the fifth transistor 8, the fifth transistor 8 becomes conductive. Similarly, when the voltage of the product of the collector current of the third transistor 5 and the seventh resistor 20 exceeds the V _BE of the tenth transistor 10, the tenth transistor 10 becomes conductive, and as a result, the output terminal 11 10th transistor 1
A saturation voltage V _CESAT (hereinafter referred to as V _CESAT ) of 0 is output (hereinafter referred to as the set state). On the other hand, the sixth transistor 9 is connected to the reset terminal 2.
When a voltage equal to or higher than V _BE is input, the sixth transistor 9 becomes conductive, the fifth transistor 8 becomes cut off, and since no current flows through the current mirror circuit, the tenth transistor 10 also becomes cut off. As a result, a voltage close to the power supply voltage is output from the output terminal 11 (hereinafter this will be referred to as a reset state).

Problems to be Solved by the Invention In such a conventional bistable multivibrator circuit, when short-term noise is input to the set input terminal 1 or the reset input terminal 2, the noise causes the fourth transistor 7 or the This causes a malfunction in which the transistor 9 of No. 6 becomes conductive and the output voltage of the output terminal 11 is reversed.
It was necessary to insert a low-pass filter into the set input terminal 1 and the reset input terminal 2 to remove noise components. Further, there is a problem that malfunctions are likely to occur when noise enters the power supply terminal 12 or the reference potential, and when used in a strong electric field, high frequency currents are induced on the wiring, resulting in malfunctions.

SUMMARY OF THE INVENTION The present invention is intended to solve these conventional problems, and an object of the present invention is to provide a bistable multivibrator circuit that is not affected by noise components even if a signal containing noise components is input to the set terminal or reset terminal. shall be.

Means for Solving the Problem In order to solve this object, the present invention connects a capacitor between the collector of the third transistor constituting a current mirror circuit and a reference potential, and divides the voltage between both terminals of the capacitor. The divided potential of two resistors connected in the same manner is inputted to the base of the eighth transistor, a constant current source and the bases of the seventh and ninth transistors are connected to the collector of the eighth transistor, and Connect the collector of the second transistor constituting the current mirror circuit to the collector of the transistor No. 9, the base of the fifth transistor, and the collector of the sixth transistor, and connect the emitters of the seventh, eighth, and ninth transistors. The collector of the seventh transistor is connected to the fourth resistor connected to the power supply terminal and the base of the tenth transistor, and the emitter of the tenth transistor is connected to the reference potential. The collector of the transistor is connected to a fifth resistor connected between the power supply terminal and the output terminal.

Effect: With this configuration, the output terminal will not enter the set state unless a voltage higher than V _BE continues to be input for a certain period of time from the moment the set input terminal reaches a voltage higher than V _BE of the fourth transistor. Also, regarding the reset input terminal, unless the input terminal continues to input a voltage higher than V _BE of the sixth transistor 9 for a certain period of time, the output terminal will not enter the reset state. Therefore, even if an input signal containing a noise component for a certain period of time or less is input to the set input terminal or the reset input terminal, the set input terminal and the reset input terminal are not affected by the noise component. This also applies to noise at the power supply terminal and reference potential.

Examples Examples of the present invention will be described below with reference to FIG. In FIG. 1, elements having the same functions as those in FIG. 2 are given the same reference numerals, and their explanations will be omitted. 13
is a capacitor connected between the collector of the third transistor 5 and the reference voltage terminal; 14 and 15 are second and third capacitors that divide the voltage across the capacitor 13;
The resistor 16 is an eighth transistor whose base is connected to the voltage divided by the second and third resistors, and whose collector is connected to the constant current source 17 and the bases of the ninth and seventh transistors. be. Reference numeral 18 denotes a ninth transistor whose base is connected to the collector of the eighth transistor 16 and whose collector is connected to the collectors of the second and sixth transistors 4 and 9 and the base of the fifth transistor 8.
A seventh transistor 21 has a base connected to the collector of the eighth transistor 16, and a collector connected to one end of the fourth resistor 22 and the base of the tenth transistor 10. A fourth resistor 22 has one end connected to the power supply terminal 12 and the other end connected to the collector of the seventh transistor 21 and the base of the tenth transistor 10.

In the above circuit, when a voltage higher than V _BE of the fourth transistor is input to the set input terminal 1, the fourth transistor
The transistor 7 becomes conductive and the first resistor 6
As a result, current flows through the collectors of the first, second, and third transistors 3, 4, and 5 that constitute the current mirror circuit. The collector current of the third transistor 5 charges the capacitor 13, and the terminal voltage of the capacitor 13 increases. As a result, the base voltage of the eighth transistor 16 increases and when it reaches V _BE or higher, the eighth transistor 16 becomes conductive.
As a result, the ninth transistor 18 is turned off, the collector current of the second transistor 4 flows into the base of the fifth transistor 8, the fifth transistor 8 is turned on, and the current continues to flow through the current mirror circuit. flows. At the same time, the seventh transistor 21 is turned off, the tenth transistor 10 is turned on, and V _CESET is output to the output terminal 11, resulting in a set state. On the other hand, if a voltage higher than V _BE is input to reset terminal 2, the 6th
The transistor 9 becomes conductive, the fifth transistor 8 becomes cut off, and no current flows through the current mirror circuit. Therefore, the capacitor 13 is discharged by the second and third resistors 14 and 15, and the fifth transistor 8 is cut off. The terminal voltage gradually decreases. When the base potential of the eighth transistor 16 falls below V _BE , the eighth transistor 16 is cut off, the current of the constant current source 17 makes the ninth transistor 18 and the seventh transistor 21 conductive, and the fifth transistor 8 maintains the cut-off state,
No current flows through the current mirror circuit. At the same time, the tenth transistor 10 is cut off, and the output terminal 11 outputs a voltage close to the power supply voltage, resulting in a reset state. A timing chart representing the above operation is shown in FIG.

Effects of the Invention As described above, the present invention requires a certain period of time for the capacitor to be charged after a voltage higher than V _BE is applied to the reset input terminal until the circuit enters the set state, and also requires a certain period of time for the capacitor to be charged until the circuit enters the set state. After a voltage higher than _BE is applied, a certain amount of time is required for the capacitor to discharge until the circuit is reset. Therefore, even if the set and reset input signals contain a large amount of noise components, it is possible to construct a bistable multivibrator that can operate stably without being affected by the noise components.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram of a bistable multivibrator according to an embodiment of the present invention, Fig. 2 is a circuit diagram of a conventional bistable multivibrator circuit, and Fig. 3 is a timing diagram showing the operation of Figs. 1 and 2. It's a chat. 1... Set input terminal, 2... Reset input terminal, 3... First transistor, 4... Second transistor, 5... Third transistor, 6...
First resistor, 7...Fourth transistor, 8...
5th transistor, 9...6th transistor, 10...10th transistor, 11...output terminal, 12...power supply terminal, 13...capacitor,
14...Second resistance, 15...Third resistance, 16
...Eighth transistor, 17... Constant current source, 1
8... Ninth transistor, 19... Sixth resistor, 20... Seventh resistor, 21... Seventh transistor, 22... Fourth resistor, 23... Fifth resistor.

Claims (1)

[Claims] 1 The first, second, and
A first resistor is connected to the collector of the first transistor of the third transistors, the collectors of the fourth and fifth transistors are connected to the other end of the first resistor, and the base of the fourth transistor is connected to the collector of the first transistor of the third transistor. A set signal input section is connected to the terminal, a reference potential section is connected to the emitter, and the collector of the second transistor constituting the current mirror and the sixth and ninth transistors are connected to the base of the fifth transistor. and a reference potential section is connected to the emitter of the fifth transistor,
A reset signal input section is connected to the base of the sixth transistor, a reference potential section is connected to the emitter of the sixth transistor, and the collector of the eighth transistor is connected to the base of the ninth transistor. The base of the seventh transistor and the constant current source are connected to each other, the emitters of the seventh, eighth and ninth transistors are connected to a reference potential part, and the collector of the seventh transistor is connected to the base of the tenth transistor and the constant current source. The other end of the fourth resistor is connected to a power supply terminal, the collector of the tenth transistor is connected to an output terminal and a fifth resistor, and the other end of the fifth resistor is connected to the collector of the tenth transistor. is connected to the power supply terminal, a capacitor is connected between the collector of the third transistor constituting the current mirror and the reference potential, and second and third resistors are provided to divide the voltage across the capacitor. A bistable multivibrator configured to input the potential divided by the second and third resistors to the base of the eighth transistor.