JPH0212840A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH0212840A
JPH0212840A JP16301388A JP16301388A JPH0212840A JP H0212840 A JPH0212840 A JP H0212840A JP 16301388 A JP16301388 A JP 16301388A JP 16301388 A JP16301388 A JP 16301388A JP H0212840 A JPH0212840 A JP H0212840A
Authority
JP
Japan
Prior art keywords
lead frame
semiconductor
semiconductor chip
magnetic
wafer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16301388A
Other languages
Japanese (ja)
Inventor
Osamu Hirohashi
広橋 修
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP16301388A priority Critical patent/JPH0212840A/en
Publication of JPH0212840A publication Critical patent/JPH0212840A/en
Pending legal-status Critical Current

Links

Landscapes

  • Die Bonding (AREA)

Abstract

PURPOSE:To dissolve warp and internal stress caused by heat in a die bonding process by a simple process, by a method wherein, after a magnetic film is formed on the rear of a semiconductor wafer and magnetized, the wafer is divided into semiconductor chips by dicing, the chip is mounted on a lead frame made of magnetic material provided with a die pad, and fixed thereon by magnetic force. CONSTITUTION:After a magnetic film 3 is formed on the rear of a semiconductor wafer and magnetized, the wafer is divided into chips 11 by dicing it. The semiconductor chip 11 is mounted on a lead frame 13 made of magnetic material provided with a die pad 14, and fixed by magnetic force. The above semiconductor 11 and lead frame terminals 15 are wire-bonded, and then molded in a body with mold resin 19. For example, when the attractive force is small as compared with the operating force at the time of bonding, the attractive force is reinforced by a magnet 18. Thereby, treatments such as injection of adhesive agent or solder and its heating are made unnecessary, the process is shortened, and the warp and the internal stress caused by heat based on the difference of thermal expansion coefficients between the semiconductor chip and the lead frame, can be eliminated.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、半導体装置、特に半導体集積回路装置の製
造方法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, particularly a semiconductor integrated circuit device.

〔従来の技術〕[Conventional technology]

第2図は従来の半導体集積回路装置の一工程における状
態を示す斜視図である。半導体ウェハをダイジングして
得られる半導体チップ1はリードフレーム6のダイパッ
ド2の上に接着剤3によって固定される。この固定は、
接着剤3による樹脂接着のほか、半田付けによる半田接
合、金とシリコンの共晶による共晶接合等がある。この
ように半導体チップlがリードフレーム6に固定された
後、ワイヤボンディング装置を使用し、金線等のワイヤ
4によって半導体チップ1とリードフレーム端子5を接
続する。図はこの状態を示す。その後半導体チップ1と
リード、フレーム6とは図示しないモールド樹脂により
モールドされる。
FIG. 2 is a perspective view showing a state of a conventional semiconductor integrated circuit device in one step. A semiconductor chip 1 obtained by dicing a semiconductor wafer is fixed onto a die pad 2 of a lead frame 6 with an adhesive 3. This fixation is
In addition to resin bonding using the adhesive 3, solder bonding using soldering, eutectic bonding using eutectic gold and silicon, etc. are available. After the semiconductor chip 1 is fixed to the lead frame 6 in this manner, the semiconductor chip 1 and the lead frame terminals 5 are connected by wires 4 such as gold wires using a wire bonding device. The figure shows this situation. Thereafter, the semiconductor chip 1, leads, and frame 6 are molded with a molding resin (not shown).

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

前記の従来の製造方法は、半導体チップ1とダイパッド
2とをダイボンディングするために(a)樹脂接着、(
b)半田接合、(C)共晶接合等を採用する。(a)は
樹脂の硬化のために150゛〜200℃、(b)は25
0”〜350℃、(c)は320°〜450℃の高温が
半導体チップ1に加わる。そのために半導体チップ1と
ダイパッド2の熱膨張係数の差により、バイメタルと同
じ原理で半導体チップ1にそりと内部応力が生じ、半還
体チップ1にクラックが発生する恐れがあるという問題
がある。
The conventional manufacturing method described above includes (a) resin bonding, (
b) Solder bonding, (C) Eutectic bonding, etc. are used. (a) is 150° to 200°C for curing the resin, (b) is 25°C.
0" to 350°C, and (c) a high temperature of 320° to 450°C is applied to the semiconductor chip 1. Therefore, due to the difference in thermal expansion coefficient between the semiconductor chip 1 and the die pad 2, the semiconductor chip 1 warps on the same principle as bimetal. There is a problem in that internal stress is generated and cracks may occur in the semicircular chip 1.

この発明の目的は、グイボンディング工程の熱によるそ
りと内部応力を解消した簡単な工程の半導体装置の製造
方法を提供しようとするものである。
SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device using a simple process that eliminates warpage and internal stress caused by heat in the bonding process.

〔課題を解決するための手段〕[Means to solve the problem]

この発明は、半導体ウェハの裏面に磁性膜を形成し磁化
してからダイジングにより半導体チップに分割し、この
半導体チップをダイパッドを備えた磁性材よりなるリー
ドフレームに搭載して磁力により固定し、前記半導体チ
ップとリードフレーム端子との間をワイヤボンディング
し、しかる後前記半導体チップと前記リードフレームと
を一体にモールド樹脂でモールドするものである。
This invention involves forming a magnetic film on the back surface of a semiconductor wafer, magnetizing it, dividing it into semiconductor chips by dicing, mounting the semiconductor chips on a lead frame made of a magnetic material with a die pad, and fixing them by magnetic force. Wire bonding is performed between the semiconductor chip and the lead frame terminal, and then the semiconductor chip and the lead frame are integrally molded with a molding resin.

〔作用〕[Effect]

この発明によれば半導体チップは、接着及び加熱等によ
らず、半導体チップNの裏面の磁性膜とダイパッドとの
間で単に磁力により吸着され、固定され、ワイヤボンデ
ィングされ、しかるのちリードフレームと共にモールド
樹脂によりモールドされるので、従来のように接着や加
熱により半導体チップに熱が加わることがなく、それに
よりそりや内部応力により半導体チップにクラックが入
るようなことがない。
According to this invention, the semiconductor chip is simply attracted and fixed by magnetic force between the magnetic film on the back surface of the semiconductor chip N and the die pad without using adhesive or heating, and wire bonded, and then molded together with a lead frame. Since the semiconductor chip is molded with resin, heat is not applied to the semiconductor chip due to adhesion or heating unlike in the past, and therefore there is no possibility of warping or cracking of the semiconductor chip due to internal stress.

〔実施例〕〔Example〕

第1図はこの発明の実施例の工程図であり、(イ)は半
導体チップをグイパッド上に位置決めさせたところ、(
ロ)はワイヤボンディング工程、(ハ)はモールドを完
了した半導体装置を示す。
FIG. 1 is a process diagram of an embodiment of the present invention, and (a) shows a semiconductor chip positioned on a guide pad (
(b) shows the wire bonding process, and (c) shows the semiconductor device after the molding process has been completed.

図面に示す工程に先立ち、公知のウェハプロセスを経過
した半導体ウェハは、その裏面に磁性膜が形成され、磁
化される。この磁性膜は磁性材料をスパッタによって形
成するが、磁性粉末を主成分とする塗料を塗布してもよ
い。その後、半導体ウェハをダイジングしてチップ化す
る。
Prior to the steps shown in the drawings, a semiconductor wafer that has undergone a known wafer process has a magnetic film formed on its back surface and is magnetized. This magnetic film is formed by sputtering a magnetic material, but a paint containing magnetic powder as a main component may also be applied. Thereafter, the semiconductor wafer is diced into chips.

第1図の工程(イ)に示すように、チップ化した半導体
チップ11はその磁化された裏面の磁性膜12を427
0イ等の磁性材からなる薄板を打ち抜いたリードフレー
ム13のダイパッド14の所定の位置に当接される。こ
うして半導体チップ11をダイパッド14に磁力により
吸着させ固定させる。なお15はグイパッド14と一体
にされたリードフレーム端子である。
As shown in step (a) of FIG.
It is brought into contact with a predetermined position of a die pad 14 of a lead frame 13 punched out of a thin plate made of a magnetic material such as 0I. In this way, the semiconductor chip 11 is magnetically attracted and fixed to the die pad 14. Note that 15 is a lead frame terminal integrated with the guide pad 14.

(ロ)のワイヤボンディング工程において、ワイヤボン
ディング装置のテーブル16の上で前記グイパッド14
に吸着されている半導体チップ11とリードフレーム端
子15とをキャピラリ17から操り出される金線等のワ
イヤ4で接続する。ワイヤボンディング操作力に対し磁
力による吸着が弱い時には、磁石18で補強する。また
ダイパッド14とテーブル16に孔を設けて真空力で吸
着力を補強してもよい。
In the wire bonding step (b), the gui pad 14 is placed on the table 16 of the wire bonding machine.
A wire 4 such as a gold wire drawn out from a capillary 17 connects the semiconductor chip 11 which is attracted to the lead frame terminal 15 to the lead frame terminal 15 . When the magnetic attraction is weak against the wire bonding operation force, the magnet 18 is used to reinforce it. Alternatively, holes may be provided in the die pad 14 and the table 16 to reinforce the suction force using vacuum force.

(ロ)に示すように、磁力で吸着されたままのワイヤボ
ンディングされたリードフレーム13と半導体チップ1
1は、トランスファモールドマシン等によりリードフレ
ーム端子15を外に出してモールド樹脂19でモールド
される。モールド時の樹脂の流動圧によって半導体チッ
プ11とリードフレーム13との吸着による相対位置が
ずれないようにする必要があるが、これはモールドの一
般的技術により極めて容易に達成される。その時、半導
体チップ11とリードフレーム13とを接続するワイヤ
4の数が多い時にはかなり貢献する。
As shown in (b), the wire-bonded lead frame 13 and the semiconductor chip 1 are still attracted by magnetic force.
1 is molded with mold resin 19 using a transfer molding machine or the like with lead frame terminals 15 exposed. Although it is necessary to prevent the relative positions of the semiconductor chip 11 and the lead frame 13 from shifting due to adsorption due to the flow pressure of the resin during molding, this can be achieved extremely easily using common molding techniques. At that time, when the number of wires 4 connecting the semiconductor chip 11 and the lead frame 13 is large, this contributes considerably.

前記工程の変形を証明する。半導体チップ11の裏面の
磁性膜12を磁化する代りに、リードフレーム13、特
にそのダイパッド14の部分を磁化してもよいし、双方
を磁化してもよい。また磁石18を使用する場合には、
テーブル16に磁化されていないリードフレーム13を
載せ、磁化されていない半導体チップ1−1を位置決め
して置き、磁石18の磁力で両者をはじめて磁化して吸
着し、ただちにワイヤボンディングを行ってもよい。こ
の場合、グイボンディング工程はワイヤボンディング工
程に完全に吸収され、実質上は無に等しい。
A variation of the above process is demonstrated. Instead of magnetizing the magnetic film 12 on the back surface of the semiconductor chip 11, the lead frame 13, particularly the die pad 14 thereof, may be magnetized, or both may be magnetized. In addition, when using the magnet 18,
Alternatively, the unmagnetized lead frame 13 is placed on the table 16, the unmagnetized semiconductor chip 1-1 is positioned and placed, and both are magnetized and attracted for the first time by the magnetic force of the magnet 18, and wire bonding is performed immediately. . In this case, the wire bonding process is completely absorbed into the wire bonding process and is essentially nothing.

〔発明の効果〕〔Effect of the invention〕

この発明は、半導体ウェハの裏面に磁性膜を形し磁化し
てからダイジングにより半導体チップに分割し、この半
導体チップをダイパッドを備えた磁性材よりなるリード
フレームに搭載して磁力により固定し、前記半導体チッ
プとリードフレーム端子との間をワイヤボンディングし
、しかる後前記半導体チップと前記リードフレームとを
一体にモールド樹脂でモールドするようにしたので、従
来のダイボンディングのような接着剤又は半田の注入と
その加熱という処理がなくなって、工程が節潔かつ短縮
されるという効果がある。また加熱処理がなく磁力によ
る吸着であるから、半導体チップとリードフレームとの
熱膨張係数の差に基く熱によるそりと内部応力が全く発
生せず、クラック等の不良が無くなって品質と歩留りが
向上するという効果がある。
This invention forms a magnetic film on the back surface of a semiconductor wafer, magnetizes it, divides it into semiconductor chips by dicing, mounts this semiconductor chip on a lead frame made of a magnetic material with a die pad, and fixes it by magnetic force. Wire bonding is performed between the semiconductor chip and the lead frame terminal, and then the semiconductor chip and the lead frame are integrally molded with molding resin, so there is no need to inject adhesive or solder as in conventional die bonding. This eliminates the need for heating and heating, which has the effect of simplifying and shortening the process. In addition, since there is no heat treatment and the adsorption is done by magnetic force, there is no warping or internal stress caused by heat due to the difference in thermal expansion coefficients between the semiconductor chip and the lead frame, eliminating defects such as cracks and improving quality and yield. It has the effect of

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの発明の実施例の工程図、第2図は従来の技
術例の斜視図である。 1.11・・・半導体チップ、2,4・・・グイパッド
、3・・・接着剤、6,13・・・リードフレーム、1
2・・・篩 図 第 図
FIG. 1 is a process diagram of an embodiment of the present invention, and FIG. 2 is a perspective view of a conventional technique. 1.11... Semiconductor chip, 2, 4... Gui pad, 3... Adhesive, 6, 13... Lead frame, 1
2...Sieve diagram

Claims (1)

【特許請求の範囲】[Claims] 1)半導体ウェハの裏面に磁性膜を形成し磁化してから
ダイジングにより半導体チップに分割し、この半導体チ
ップをダイパッドを備えた磁性材よりなるリードフレー
ムに搭載して磁力により固定し、前記半導体チップとリ
ードフレーム端子との間をワイヤボンディングし、しか
る後前記半導体チップと前記リードフレームとを一体に
モールド樹脂でモールドすることを特徴とする半導体装
置の製造方法。
1) Form a magnetic film on the back surface of a semiconductor wafer, magnetize it, divide it into semiconductor chips by dicing, mount this semiconductor chip on a lead frame made of a magnetic material with a die pad, fix it by magnetic force, and divide the semiconductor wafer into semiconductor chips. 1. A method of manufacturing a semiconductor device, comprising wire bonding between the semiconductor chip and the lead frame terminal, and then molding the semiconductor chip and the lead frame together with a molding resin.
JP16301388A 1988-06-30 1988-06-30 Manufacture of semiconductor device Pending JPH0212840A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16301388A JPH0212840A (en) 1988-06-30 1988-06-30 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16301388A JPH0212840A (en) 1988-06-30 1988-06-30 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH0212840A true JPH0212840A (en) 1990-01-17

Family

ID=15765539

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16301388A Pending JPH0212840A (en) 1988-06-30 1988-06-30 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH0212840A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0418298A (en) * 1990-05-02 1992-01-22 Fuji Plant Kogyo Kk Automatic oil feeding and controlling method for automobile
KR19990040606A (en) * 1997-11-19 1999-06-05 윤종용 Semiconductor chip package
JP2006317321A (en) * 2005-05-13 2006-11-24 Denso Corp Physical quantity sensor device
US10629465B2 (en) 2018-05-28 2020-04-21 Besi Switzerland Ag Method for calibrating a component mounting apparatus
US12167542B2 (en) 2020-11-09 2024-12-10 Tokyo Electron Limited Method for manufacturing substrate with sensor

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0418298A (en) * 1990-05-02 1992-01-22 Fuji Plant Kogyo Kk Automatic oil feeding and controlling method for automobile
KR19990040606A (en) * 1997-11-19 1999-06-05 윤종용 Semiconductor chip package
JP2006317321A (en) * 2005-05-13 2006-11-24 Denso Corp Physical quantity sensor device
US10629465B2 (en) 2018-05-28 2020-04-21 Besi Switzerland Ag Method for calibrating a component mounting apparatus
US12167542B2 (en) 2020-11-09 2024-12-10 Tokyo Electron Limited Method for manufacturing substrate with sensor

Similar Documents

Publication Publication Date Title
US7202107B2 (en) Method for producing a semiconductor component with a plastic housing and carrier plate for performing the method
US20080187613A1 (en) Method of manufacturing wafer-level chip-size package and molding apparatus used in the method
JP4595265B2 (en) Manufacturing method of semiconductor device
JPH1117105A (en) Semiconductor package structure using epoxy molding compound pad and method of manufacturing epoxy molding compound pad
JPH1140738A (en) Semiconductor device
CN115116860A (en) Chip packaging method and chip
JPH0212840A (en) Manufacture of semiconductor device
JP2581748B2 (en) Lead wire bonding apparatus and method
JPH10326800A (en) Method for manufacturing semiconductor device and mold for semiconductor manufacturing device
JP3531580B2 (en) Bonding method
JPS59181025A (en) Semiconductor device
US6869832B2 (en) Method for planarizing bumped die
JP2000349099A (en) Solder joining method and semiconductor device manufacturing method
JP2008545254A (en) Magnetic assisted manufacturing to reduce mold flash and support using heat slag assembly
JPH04299848A (en) Semiconductor device and its manufacture
JPH06314708A (en) Semiconductor manufacturing apparatus and method of manufacturing semiconductor device
JPH03284857A (en) Manufacture of semiconductor device
JP3012643B1 (en) Method for manufacturing semiconductor device
JP2000252310A (en) Molding method and apparatus, and method of manufacturing semiconductor device using the same
JPH04247640A (en) Manufacture of semiconductor device
JPH04211998A (en) Production of semiconductor device and semiconductor device production device
JPH06349870A (en) Semiconductor device and manufacturing method thereof
JP2001176890A (en) Semiconductor device and method of manufacturing semiconductor device
JPH0669252A (en) Manufacture of semiconductor device
JPH0397253A (en) Lead frame for integrated circuit