JPH0214071U - - Google Patents
Info
- Publication number
- JPH0214071U JPH0214071U JP9174288U JP9174288U JPH0214071U JP H0214071 U JPH0214071 U JP H0214071U JP 9174288 U JP9174288 U JP 9174288U JP 9174288 U JP9174288 U JP 9174288U JP H0214071 U JPH0214071 U JP H0214071U
- Authority
- JP
- Japan
- Prior art keywords
- output
- dut
- comparator
- signal
- level
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Measurement Of Current Or Voltage (AREA)
- Manipulation Of Pulses (AREA)
- Electronic Switches (AREA)
Description
第１図は本考案に係る比較回路の一実施例を示
す図、第２図は本考案に係る別の構成例を示す図
、第３図は第１図回路の真理値表を示す図、第４
図は第１図及び第２図のタイムチヤートである。
１，２……コンパレータ、３……ゲート、７…
…セレクタ、８……プロセツサ。
FIG. 1 is a diagram showing one embodiment of a comparison circuit according to the present invention, FIG. 2 is a diagram showing another configuration example according to the present invention, and FIG. 3 is a diagram showing a truth table of the circuit shown in FIG. 1. Fourth
The figure is a time chart of FIGS. 1 and 2. 1, 2...Comparator, 3...Gate, 7...
...Selector, 8...Processor.
Claims (1)
ｖｉｃｅ Ｕｎｄｅｒ Ｔｅｓｔ）からある期間
ごとにＨＩＧＨレベル、ＭＩＤＤＬＥレベル、Ｌ
ＯＷレベルをそれぞれ指令して出力させる手段と
、 ＤＵＴ出力のＨＩＧＨレベルと基準電圧ＶＨと
を比較する第１のコンパレータ１と、 ＤＵＴ出力のＬＯＷレベルと基準電圧ＶＬとを
比較する第２のコンパレータ２と、 第１と第２のコンパレータの出力信号の論理積
をとるゲート手段と、 ＤＵＴがＬＯＷレベルの信号を出力した期間は
第２のコンパレータの出力に基づく信号を出力し
、ＤＵＴがＭＩＤＤＩＥレベルの信号を出力した
期間はゲート手段の出力に基づく信号を出力し、
ＤＵＴがＨＩＧＨレベルの信号を出力した期間は
第１のコンパレータの出力に基づく信号を出力す
る手段と、 を備えた比較回路。[Scope of claim for utility model registration] Logic element to be tested (hereinafter referred to as DUT: De
vice Under Test), HIGH level, MIDDLE level, L
A means for commanding and outputting the OW level, a first comparator 1 that compares the HIGH level of the DUT output and the reference voltage VH, and a second comparator 2 that compares the LOW level of the DUT output and the reference voltage VL. and gate means for ANDing the output signals of the first and second comparators; and a gate means that outputs a signal based on the output of the second comparator during a period in which the DUT outputs a LOW level signal, and the DUT outputs a signal based on the output of the second comparator, and the DUT outputs a signal at the MIDDIE level. During the period in which the signal is output, a signal based on the output of the gate means is output,
A comparison circuit comprising: means for outputting a signal based on the output of the first comparator during a period when the DUT outputs a HIGH level signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9174288U JPH0214071U (en) | 1988-07-11 | 1988-07-11 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9174288U JPH0214071U (en) | 1988-07-11 | 1988-07-11 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0214071U true JPH0214071U (en) | 1990-01-29 |
Family
ID=31316208
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9174288U Pending JPH0214071U (en) | 1988-07-11 | 1988-07-11 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0214071U (en) |
-
1988
- 1988-07-11 JP JP9174288U patent/JPH0214071U/ja active Pending
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