JPH02140942A - Manufacture of semiconductor device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to field effect transistors, particularly semi-insulating GaAs
The present invention relates to a method for manufacturing a gate electrode and a gate recess region of a field effect transistor (hereinafter referred to as MESFET) having a Schottky junction formed on a substrate. In detail, the MESFE has a two-stage recess structure in the gate part.
The present invention relates to a method of manufacturing a MESFET in which the gate electrode is not located in the center but is close to either the source electrode or the drain electrode, and the gate electrode is asymmetric within the recess region.

BACKGROUND OF THE INVENTION MESFETs using a semi-insulating GaAs substrate on which an epitaxial layer is deposited exhibit high gain and low noise even at high frequencies of 10G82 or higher, and are used as main elements in satellite communications and the like.

-fi, the noise value of MESFET varies depending on parameters such as gate resistance and transconductance, but it also varies greatly depending on another important parameter, leakage current between the gate and drain and source resistance. In order to reduce noise, it is necessary to reduce leakage current and improve the breakdown voltage between the gate and drain of the MESFET. In addition, it is necessary to improve the breakdown voltage and reduce the source resistance at the same time.

In particular, in MESFETs using semi-insulating GaAs substrates with epitaxial layers deposited on them, N4-type GaAs is used to reduce source resistance and to obtain good ohmic contact between the source and drain electrodes and the active layer.
A low-resistance N3 layer consisting of
A commonly used method is to form a layer with a thickness of about 0.2 μm and to recess-etch this layer only in the vicinity of the gate electrode.

Furthermore, an asymmetric gate MESFET in which the gate electrode is not located in the central part of the recessed region but close to the source electrode
is proposed. However, in such a structure, the distance between the low-resistance N4 layer in the source or drain region and the gate electrode becomes abnormally close due to process variations, that is, mask alignment errors, causing a drop in breakdown voltage and leakage current. Ta. In addition, in order to further reduce the source resistance, a low resistance N” located near the gate electrode is used.
A MESFET with a two-stage recess structure for ff has also been proposed, but in this case as well, the distance between the low resistance N'E and the gate electrode becomes abnormally close due to process variations, that is, mask alignment errors, resulting in a drop in breakdown voltage and This caused an IJ current.

FIG. 3 is a process sectional view showing a conventional method of manufacturing a MESFET having a two-stage recess structure in a low resistance N-layer next to a gate electrode. MES using GaAs as a semiconductor device
An explanation will be added using FET as an example.

In Fig. 3a), on the main surface side of the semi-insulating GaAs substrate 1, an N-type active layer 2, which becomes a channel of a field effect transistor, and a low-resistance N layer to reduce source and drain resistance are formed by a normal epitaxial method. 3 are deposited successively. After a first drain electrode 4 and a first source electrode 5 are patterned on the low resistance N4 layer 3, a first insulating film 7 is deposited over the entire surface. FIG. 3b) shows a step in which a resist 8 is applied to the entire surface of the first insulating film 7 and a resist opening 9 is formed using a normal photo process. FIG. 3C) is a step in which an etching window 9-1 is opened in the first insulating film 7 by a method such as dry etching to expose a part of the low resistance N' layer 3, that is, a region where a gate will be formed. Figure 3(d)
3(c) is a step of etching the low resistance N9 layer 3 from the etching window 9-1 formed in FIG. 3(c) to form the first recess region 11. At this time, the depth of the first recess region 11 may be up to about half the depth of the low resistance N layer 3. FIG. 3(e) shows a step in which after the first insulating film 7 is completely removed, a second insulating film 26 is deposited on the surface again to form an opening. Since the MESFET has a two-stage recess structure, this etching window 9-1 is formed within the first recess region 11.

FIG. 3(f) shows a step of etching the low resistance N1 layer 3 again through the etching window 9-1 created in the second insulating film 26 in FIG. 3(e) to form the second recess region 13. As a result, the low resistance N layer 3 is divided into a source region and a drain region, which function to reduce the source resistance and drain resistance, respectively. FIG. 3g) is a step of forming the gate electrode 14 in the second recess region 13. FIG. 3(h) shows that the first drain electrode 4 and the first source electrode 5 have second electrodes, respectively.
This is a step in which the drain electrode 16 and the second source electrode 15 are added to form bowed electrodes to complete the MESFET.

The second drain electrode 16 and the second source electrode 15 are formed of gold plating or the like.

Figure 4 shows an ME of an asymmetric gate in which the conventional gate electrode is not located in the center of the recess region but close to the source electrode.
FIG. 3 is a process cross-sectional view showing a method for manufacturing an SFET. An explanation will be added using an example of a MESFET using GaAs as a semiconductor device. In FIG. 4, the same numbers or symbols are used for parts equivalent to those in FIG. 3. Figure 4(a), Figure 4(b) and Figure 4(c) are similar to Figure 3(a).
Although the steps are exactly the same as those in FIGS. 3(b) and 3(c), and a detailed explanation will be omitted, an etching window 9-1 is formed in the first insulating film 7 in FIG. 4(c). Figure 4(d)
The recessed region 27 is etched by etching the low resistance N'Ji 13 from the etching window 9-1 created in FIG. 4(C).
This is a step in which the source and drain regions are divided into source and drain regions.

FIG. 4(e) shows that the second insulating film 7 is completely removed after the first insulating film 7 is completely removed.
An insulating film 26 is deposited and an offset etching window 28 is opened in the recess region 27. Offset etching window 2
8 is not located at the center of the recess region 27 but is provided at a position closer to the source region side.

By arranging the gate electrode closer to the source region in this way, an attempt is made to ensure low source resistance and high drain breakdown voltage with little leakage current.

FIG. 4(f) shows a step of forming an offset gate electrode 25 in the offset etching window 28 provided in FIG. 4(e). FIG. 4(g) shows a MESFET in which a second drain electrode 16 and a second source electrode 15 are added to the first drain electrode 4 and the first source electrode 5, respectively, to serve as extraction electrodes.
This process is almost the same as the process shown in FIG. 3(h). Second drain electrode 16 and second source electrode 1
5 is formed with gold plating or the like.

Problems to be Solved by the Invention In the conventional semiconductor device manufacturing method shown in Figure 3, the breakdown voltage between the gate and the drain and the breakdown voltage between the gate and the source are not stable, and if these values are small, leakage current occurs. Many noises occurred, making it difficult to reduce the noise. That is, as shown in FIG. 3(e), the second etching window 9-1
This is because the process is performed using alignment marks rather than self-alignment, and therefore tends to be closer to the source or drain side.

In addition, as shown in FIG. 3(e), the second etching window 9-1 is provided inside the first recess region 11 which has been hollowed out one step, so that when cutting out a fine line width in the photolithography process, the window is not opened. There was also the problem that the gate electrode could not be formed later due to incomplete formation. For example, in the case of a MESFET using GaAs, the line width of the gate electrode is 0.
The line width is approximately 25 μm, and it is extremely difficult to provide such a fine line width inside the first recess region 11 which has been hollowed out one step. Furthermore, in the step of forming the etching window 9-1 as shown in FIG. 3(e), a dry etching method such as dry etching is normally used, but the GaAs substrate is damaged in this step and the noise value is reduced. There were also problems with the size.

Further, in the conventional method for manufacturing a semiconductor device shown in FIG. 4, the breakdown voltage between the gate and the drain and the breakdown voltage between the gate and the source are also unstable, making it difficult to reduce noise.

Furthermore, if an attempt is made to secure and stabilize the breakdown voltage, the source resistance and drain resistance increase, and it is also difficult to reduce noise. As shown in FIG. 4(8), the offset etching window 28 is formed in the recess area 27, but as in the conventional example of FIG. A major cause of instability was that the capacitance was shifted toward the side or the drain side.

On the contrary, in order to reduce the cause of this positional shift, it is necessary to increase the width of the recess region 27, for example, and it is not possible to reduce noise by reducing source resistance and drain resistance.

The present invention has been made in view of the above points, and has a high breakdown voltage between the gate and the drain, a high breakdown voltage between the gate and the source, low leakage current, stable conduction, good reproducibility, and low source resistance and drain resistance. It is an object of the present invention to provide a method for manufacturing a semiconductor device that is small and has low noise.

Means for Solving the Problems In order to solve the above problems, the present invention provides a MESFET having a two-stage recess structure in the low resistance Nφ layer of the gate electrode area, after selectively forming an underlayer SiO2 on a semiconductor substrate.
The process of depositing a first insulating film on the entire surface of the substrate and this underlayer 5i
A process of forming an opening in the first insulating film located at the center of the ns and above it, exposing a part of the semiconductor substrate, and performing a first recess etching of the semiconductor substrate from the surface; a step of removing part or all of the 5iOa by wet etching and then performing a second recess etching of the semiconductor substrate from the surface;
Steps of forming a gate electrode in an opening provided in an insulating film are sequentially performed.

In addition, in order to solve the above-mentioned problems, the present invention provides an MESFET with an asymmetric gate in which the gate electrode is not located in the center of the recess region but is close to the source electrode, after selectively forming an underlayer 5ins on the semiconductor substrate. , a step of depositing a first insulating film on the entire surface of the substrate, a step of providing an opening in the first insulating film located at the end of this underlay 5ins and the upper part thereof, and a step of depositing the underlay S i Ox remaining through this opening. A step of exposing a part of the semiconductor substrate by removing a part or the whole by wet etching, a step of performing recess etching on the semiconductor substrate from this exposed region, and forming a gate electrode in the opening provided in the first insulating film. Perform the steps sequentially.

Operation The present invention has the above-mentioned structure, and has a low resistance N of the gate electrode area.
It becomes possible to stabilize the breakdown voltage between the gate and drain and the breakdown voltage between the gate and source of a MESFET having a four-layer, two-stage recess structure, reduce leakage current, and reduce noise. That is, the process of forming the etching window for the second recess is performed in a self-aligned manner with respect to the shape of the first recess, and there is no need to use alignment marks, so the etching window may be closer to the source or drain side. This is because there is no such thing. Further, since there is no need to newly provide a fine gate window inside the first recess region which has been hollowed out, it becomes stable to cut out a fine line width in the photolithography process. Furthermore, in the final step of forming the etching window, 5id2 is partially or completely removed by wet etching instead of using a dry etching method such as normal dry etching, which causes problems such as damage to the GaAS substrate and increased noise. is also unlikely to occur.

Furthermore, the present invention has the above-described structure, which stabilizes the breakdown voltage between the gate and the drain and the breakdown voltage between the gate and the source in an asymmetric gate MESFET in which the gate electrode is not located in the center of the recessed region but is close to the source electrode. This makes it possible to reduce noise. That is, the formation of the asymmetric gate electrode, which is not located in the center of the recess region but is close to the source electrode, is performed from the same window as the etching window for the recess, and is performed in a self-aligned manner with respect to the shape of the recess. This is because there is no need to use alignment marks, so the position of the gate electrode relative to the shape of the recess is always constant. Since there is almost no displacement of the gate electrode with respect to the recess region, there is no need to increase the width of the recess region, and it is possible to reduce noise by reducing source resistance and drain resistance while ensuring breakdown voltage.

Embodiment FIG. 1 is a process sectional view of an embodiment showing a method of manufacturing a MESFET having a two-stage recess structure in the low resistance N4 layer of the gate electrode area according to the present invention. In the method of manufacturing a semiconductor device of the present invention shown in FIG. 1, parts equivalent to those in FIGS. 3 and 4 are designated by the same reference numerals.

FIG. 1(a) shows a first drain electrode 4 on a low resistance N layer 3.
After patterning the first source electrode 5 and the first source electrode 5, the underlay S
i 028) 21! This is a process of selectively leaving the electrodes on the regions where the poles are to be provided. FIG. 1(b) shows a step in which a first insulating film 7 is deposited on the entire surface and then a resist 8 is applied to form a resist opening 9. At this time, resist opening 9
is provided approximately in the center of the underlay 5iO28. Figure 1 (C
), the first insulating film 7 is etched by a method such as dry etching from the resist opening 9 formed in FIG.
In this step, a portion of the N layer 26 is removed to expose a gate forming portion of the low resistance N layer 3. Here, only the central portion of the underlay 5iO2B is etched, leaving end portions 5iO210 on both sides. In addition, by using wet etching for etching the underlying SiOxE3, the N-type active layer 2
damage can be reduced. In FIG. 1(d), a first recess region 11 is formed in the step of performing the first recess etching. FIG. 1(e) shows a step of widening the opening for the second recess etching, in which the remaining edge SiO 210 is removed by wet etching to create a cavity 12. In the embodiment shown in FIG. 1(e), the entire end portion 5iOiIO is removed, but it is not necessarily necessary to remove the entire surface, and it is sufficient if the opening is leveled to some extent. A feature of the present invention is that since the opening is expanded using wet etching, it always expands symmetrically and in self-alignment with the first recess region 11.

In FIG. 1 (f>), the second recess region 13 is formed to have a low resistance N''ff3 in the second recess etching step.

FIG. 1(g) shows a step of forming the gate electrode 14 from the substrate surface by a method such as vapor deposition. In FIG. 1(h), as the final step, a second source electrode 15 and a second drain electrode 16 are added to complete the MESFET.

As explained above with reference to FIG.
By using the ET manufacturing method, it is possible to stabilize the breakdown voltage between the gate and the drain and the breakdown voltage between the gate and the source, reduce leakage current, and reduce noise.

That is, the process of forming the etching window for the second recess is 1.
This is because the recess is self-aligned with respect to the shape of the second recess and always spreads symmetrically, so it does not lean towards the source or drain side. Also, - the first step
There is no need to provide a new window for forming a fine gate inside the recess region. Therefore, defects caused by removing fine line widths in the photolithography process are eliminated.Furthermore, the final process of forming the etching window for the recess is not a dry etching method such as normal dry etching, but a 5-inch etching process using wet etching. Since the GaAs substrate is partially or completely removed, problems such as an increase in the noise value due to damage to the GaAs substrate are unlikely to occur.

FIG. 2 is a process cross-sectional view of an embodiment showing a method of manufacturing an asymmetric gate MESFET in which the gate electrode is not located in the center of the recess region but is close to the source electrode according to the present invention. In the method for manufacturing a semiconductor device of the present invention shown in FIG. 2, parts equivalent to those in FIGS. 1, 3, and 4 are designated by the same reference numbers.

FIG. 2(a) shows the first drain electrode 4 on the low resistance N◆ layer 3.
After patterning the first source electrode 5 and the first source electrode 5, the underlay 5 is formed.
This is a step in which iCh6 is selectively left on a region where a gate electrode is to be provided. FIG. 2(b) shows that after depositing a first insulating film 7 on the entire surface, a resist 8 is applied to form an offset opening 21.
This is the process of opening a window.

At this time, the offset opening 21 is
is provided at the end near the first source electrode 5. Figure 2 (C)
2B is a step in which the first insulating film 7 is etched by a method such as dry etching to form an insulating film opening 22 through the offset opening 21 formed in FIG. 2(b). FIG. 2(d) is a step in which the underlay 5IO2B is removed by wet etching, an offset cavity 23 is formed, and a recessed portion of the low resistance N4 layer 3 is exposed. Here, the underlayer S i O *8 may be entirely removed by etching or a portion may be left on the drain electrode side. This step determines the asymmetric position of the gate electrode within the recessed region. Furthermore, damage to the N-type active layer 2 can be reduced by using wet etching for etching the underlayer 5iO26. FIG. 2e) shows a step of performing recess etching, resulting in the formation of an offset recess region 24. As shown in FIG. FIG. 2(f) shows the offset gate electrode 25.
This is a step of forming the film from the surface of the substrate by a method such as vapor deposition. FIG. 2(g) shows the second source electrode 1 as the final step.
5 and a second drain electrode 16, respectively, to form an MES.
This is the process of completing the FET.

As explained above with reference to FIG. 2, by using the manufacturing method of an asymmetric MESFET in which the gate electrode of the present invention is not located in the center of the recess region but close to the source electrode, it is possible to This makes it possible to stabilize the breakdown voltage between the gate and the source and to reduce noise. That is, the asymmetric gate electrode, which is not located in the center of the recess region but is close to the source electrode, is formed from the same window as the etching window for the recess, and is formed in a self-aligned manner with respect to the shape of the recess. This is because there is no need to use alignment marks, so the position of the gate electrode relative to the shape of the recess is always constant. In addition, the drain breakdown voltage is determined by the etching amount of the underlay 510w8 or the first underlay SfO*8
The size can be freely controlled. Furthermore, since there is almost no misalignment of the gate electrode with respect to the recess region, there is no need to increase the width of the recess region, and it is possible to reduce source resistance and noise while ensuring a high drain breakdown voltage. Furthermore, in the final step of forming the etching window, as in the present invention shown in FIG. 1, the SiO2 is partially or completely removed by wet etching instead of the usual dry etching method such as dry etching, so that the GaAs substrate is not damaged. Therefore, problems such as an increase in the noise value are less likely to occur.

Effects of the Invention As described above, the present invention brings about the following effects.

1) In a MESFET that has a two-stage recess structure in the low-resistance N4 layer of the gate electrode area, the process of forming an etching window for the second recess is performed in a self-aligned manner with respect to the shape of the first recess. There is no need to use marks. Therefore, it is possible to stabilize the breakdown voltage between the gate and the drain and the breakdown voltage between the gate and the source without leaning toward the source side or the drain side, thereby reducing leakage current and noise.

2) In a MESFET that has a two-stage recess structure in the low-resistance N-layer of the gate electrode area, there is no need to newly provide a fine gate window inside the first recess region that has been hollowed out. The line width becomes stable (later it becomes stable).

3) In an asymmetric gate MESFET in which the gate electrode is not located in the central part of the recess region but is close to the source electrode, the formation of the asymmetric gate electrode close to the source electrode is performed from the same window as the etching window for the recess. , is performed in a self-aligned manner with respect to the shape of the recess, and there is no need to use alignment marks, so that the position of the gate electrode with respect to the shape of the recess is always constant. Therefore, the breakdown voltage between the gate and the drain and the breakdown voltage between the gate and the source can be stabilized, and noise can be reduced.

4) In an asymmetric gate MESFET in which the gate electrode is not located in the center of the recessed region but close to the source electrode, there is almost no displacement of the gate electrode with respect to the recessed region, so there is no need to increase the width of the recessed region; It is possible to reduce noise by reducing source resistance while ensuring breakdown voltage.

5) In an asymmetric gate MESFET in which the gate electrode is not located in the center of the recessed region but is close to the source electrode, the drain breakdown voltage can be freely controlled by the width of the underlying SiO2 or the amount of etching thereof.

6) The final step of forming the etching window involves removing part or all of the SiO2 by wet etching instead of dry etching such as normal dry etching, which causes problems such as damage to the GaAs substrate and increased noise. is also unlikely to occur.

[Brief explanation of the drawing]

1 is a process sectional view of a method for manufacturing a semiconductor device showing a first embodiment of the present invention, FIG. 2 is a process sectional view of a method for manufacturing a semiconductor device showing a second embodiment of the invention, and FIG. Figure and 4th
The figures are process cross-sectional views of a semiconductor device manufacturing method showing first and second conventional examples. DESCRIPTION OF SYMBOLS 1...Semi-insulating GaAs substrate, active layer, 3...Φ low-resistance N-layer, 4-in electrode, 5-φ first source electrode, SiO2, 7... first insulating film, 8I 9... Resist opening, 10... 102, 11... First recess area, 12 Cavity, 13... Second recess area, 14
Gate electrode, 16... Second gate electrode,... Second
Drain electrode, 21...offset cell part, 23@.6 offset cavity, 24.offset recess area, 25.offset electrode. Name of agent: Patent attorney Shigetaka Awano Haka 1 person 2...Fist N
Mold - 1st drain 6...Bottom...Register/End part S 16/Opening spine diagram Figure 24 off t! It's been a long time since I've been in the middle of a long time since I've been in the middle of a long time since I've been in the middle of a long time since I've been in the middle of a long time.

Claims (2)

[Claims] (1) After selectively forming an underlayer SiO_2 on a semiconductor substrate, a step of depositing a first insulating film on the entire surface of the substrate, and forming an opening in the first insulating film located in the central part of the underlayer SiO_2 and above it. a step of exposing a part of the semiconductor substrate and performing a first recess etching of the semiconductor substrate from the surface;
a step of performing a second recess etching of the semiconductor substrate from the surface after removing part or all of 2 by wet etching, and a step of forming a gate electrode in the recessed region from the opening provided in the first insulating film. A method for manufacturing a semiconductor device, comprising: (2) After selectively forming an underlay SiO_2 on the semiconductor substrate, a step of depositing a first insulating film on the entire surface of the substrate, and forming an opening in the first insulating film located at the end of the underlay SiO_2 and above it. a step of removing a part or all of the underlying SiO_2 left from this opening by wet etching to expose a part of the semiconductor substrate, and performing recess etching of the semiconductor substrate from the exposed surface of the substrate. and forming a gate electrode in a recessed region from an opening provided in the first insulating film.