JPH0214143U - - Google Patents

Info

Publication number
JPH0214143U
JPH0214143U JP9069488U JP9069488U JPH0214143U JP H0214143 U JPH0214143 U JP H0214143U JP 9069488 U JP9069488 U JP 9069488U JP 9069488 U JP9069488 U JP 9069488U JP H0214143 U JPH0214143 U JP H0214143U
Authority
JP
Japan
Prior art keywords
data memory
unwritten
addresses
read
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9069488U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP9069488U priority Critical patent/JPH0214143U/ja
Publication of JPH0214143U publication Critical patent/JPH0214143U/ja
Pending legal-status Critical Current

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  • Test And Diagnosis Of Digital Computers (AREA)
  • Debugging And Monitoring (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本考案の一実施例のブロツク図、第2
図は本考案の実施例2のブロツク図である。 11……データメモリN(アドレスN)、12
……書き込み済みフラグN(アドレスN)、13
……書き込み信号、14……リセツト信号、15
……読み出し警告回路、16……読み出し信号、
17……警告信号、21……データメモリN(ア
ドレスN)、22……書き込み済みフラグN(ア
ドレスN)、23……書き込み信号、24……リ
セツト信号、25……読み出し警告回路、26…
…読み出し信号、27……警告信号、28……ブ
レーク制御回路。
Fig. 1 is a block diagram of an embodiment of the present invention;
The figure is a block diagram of Embodiment 2 of the present invention. 11...Data memory N (address N), 12
...Written flag N (address N), 13
...Write signal, 14...Reset signal, 15
...read warning circuit, 16...read signal,
17...Warning signal, 21...Data memory N (address N), 22...Written flag N (address N), 23...Write signal, 24...Reset signal, 25...Read warning circuit, 26...
...Read signal, 27...Warning signal, 28...Break control circuit.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] データメモリに対し書き込みが行なわれたアド
レスと未書き込みのアドレスとを区別するメモリ
と、未書き込みのデータメモリを読み出したこと
を検出し警告する回路を有するマイクロコンピユ
ータ開発支援装置。
A microcomputer development support device that has a memory that distinguishes between written addresses and unwritten addresses in data memory, and a circuit that detects and warns when unwritten data memory is read.
JP9069488U 1988-07-08 1988-07-08 Pending JPH0214143U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9069488U JPH0214143U (en) 1988-07-08 1988-07-08

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9069488U JPH0214143U (en) 1988-07-08 1988-07-08

Publications (1)

Publication Number Publication Date
JPH0214143U true JPH0214143U (en) 1990-01-29

Family

ID=31315207

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9069488U Pending JPH0214143U (en) 1988-07-08 1988-07-08

Country Status (1)

Country Link
JP (1) JPH0214143U (en)

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