JPH02155264A - semiconductor storage device - Google Patents

Abstract

PURPOSE:To make it possible to manufacture a high-speed, high-quality semiconductor storage device by forming a contact hole in a storage cell part in a slender pattern, and forming two or more wiring layers so as to cross the short side direction of the slender contact hole. CONSTITUTION:At first, an oxide film is formed on the surface of a P-type silicon substrate 101. Then, a silicon nitride film is formed by a CVD method. The silicon nitride film is removed, and an element isolating oxide film 103 is formed. A gate oxide film is formed at an active region other than the element isolating oxide film 103. After a polycrystalline silicon film is formed, the unnecessary part is removed by photographic etching, and a gate electrode 107 is formed. Then, N-type impurities, i.e., phosphorus impurities here, are implanted. Then, annealing is performed, and an N-type impurity layer 102 is formed. A silicon oxide film is formed. The unnecessary part of the silicon oxide film is removed, by photographic etching and a slender contact hole 105 is formed. Aluminum is formed by a sputtering method. The unnecessary part of the aluminum is removed, and aluminum wirings 106 are formed so as to cross the short side direction of the contact hole 105.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a contact hole structure for a semiconductor memory device.

[Conventional technology]

In recent years, semiconductor devices, especially semiconductor memory devices, have become increasingly finer and more highly integrated. The same is true for contact holes, whose dimensions are becoming finer down to the submicron region. Here, conventional contact holes and contact between a wiring layer and a silicon substrate will be described using FIGS. 2(a) and 2(b). FIG. 2(a) is a plan view showing a part of a memory cell of a static RAM (hereinafter referred to as SRAM), and FIG. 2(b) is a main cross-sectional view taken along A-8 in the plan view of FIG. FIG. In Figures 2(a) and (b), 20
1 is a P-type silicon substrate, 202 is an N-type impurity layer, 203
204 is a silicon oxide film for element isolation, 204 is a silicon oxide film, 205 is a contact hole, 206 is an aluminum wiring, and 207 is a gate electrode and wiring layer made of polycrystalline silicon.

An N-type impurity layer 202 formed on a silicon substrate 201 and an aluminum wiring 206 are ohmically connected through a contact hole 205 formed in a silicon oxide film 204. Contact hole 20 in memory cell
5 is “Hitachi Hyoron, V.

170, No.2. (1988-2), p98J, Figure 1
Conventionally, the contact hole was square or circular, and the width of the aluminum wiring was larger than the diameter of the contact hole.

[Problem to be solved by the invention]

Generally, a semiconductor memory device is divided into a memory cell section and a peripheral circuit section, and most of the area of a semiconductor memory device is occupied by the memory cell section. It is important to Furthermore, in order to increase the operating speed of a semiconductor memory device, it is necessary to increase the operating speed of the peripheral circuit section, and it is particularly important to reduce the contact resistance of the peripheral circuit section.

In order to miniaturize and increase the integration of semiconductor memory devices, if the conventional contact holes are made to have the same diameter in the memory cell area and the peripheral circuit area and are miniaturized to the submicron region, the following problems arise. .

When the contact diameter reaches the sub-micron range, the contact resistance, that is, the contact resistance between the semiconductor substrate and the metal electrode, increases rapidly, and in the peripheral circuit area, the contact resistance becomes greater than the resistance in the operating state of the transistor, causing the peripheral circuit area to deteriorate. The problem has been that the operating speed of the semiconductor memory device becomes slow.

Furthermore, in the conventional technology described above, when light passes through a circular or square contact hole mask in the photolithography process when forming a contact hole, the light is diffracted and the intensity of the light is weakened, so that the resist is completely exposed. However, there was a problem in that contact holes could not be formed.

Furthermore, in the prior art described above, in the aluminum sputtering process for forming an aluminum electrode after the contact hole is formed, it becomes difficult for sputtered aluminum to enter the contact hole, resulting in a thin aluminum film inside the contact hole. As a result, there have been problems in that the aluminum wiring and the silicon substrate are not connected, or that if current continues to flow through the aluminum wiring to the silicon substrate, the thin aluminum film in the contact hole is disconnected.

In addition, in the conventional technology described above, the aluminum wiring width is made larger than the contact hole diameter, and it is necessary to increase the aluminum wiring width by taking into account the alignment margin between the contact hole mask and the aluminum electrode mask, and the aluminum wiring spacing must be increased. Another problem was that it was difficult to miniaturize.

SUMMARY OF THE INVENTION The present invention aims to solve these problems, and its purpose is to provide a semiconductor device that operates at high speed even when the semiconductor memory device is miniaturized and highly integrated. It is an object of the present invention to provide a semiconductor memory device in which a contact hole can be formed even when the contact hole is miniaturized, the thickness of an aluminum film in the contact hole can be increased, and the interval between aluminum interconnections can be further miniaturized.

[Means to solve the problem]

A semiconductor memory device of the present invention includes a memory cell portion formed in a semiconductor substrate and a peripheral circuit portion, in which a contact hole formed in the memory cell portion and the peripheral circuit portion is elongated, and the contact hole formed in the memory cell portion and the peripheral circuit portion is elongated. and a wiring layer formed in the peripheral circuit section crosses in the short side direction of the elongated contact hole, and within the contact hole, the wiring layer crosses the active region formed in the memory cell section and the peripheral circuit section. The peripheral circuit portion is characterized in that the width of the active region within the contact hole is wider in the peripheral circuit portion than in the memory cell portion.

〔Example〕

Embodiments of the present invention will be described in detail using FIGS. 1(a) and 1(b). FIG. 1(a) is a plan view showing a part of a memory cell of an SRAM, and FIG. 1(b) is a main sectional view showing a cross section taken along line A-8 in the plan view of FIG. 1(a). Figure 1 (a
), (b), 101 is a P-type silicon substrate, 102
is an N-type impurity layer, 103 is a silicon oxide film for element isolation,
104 is a silicon oxide film, 105 is a contact hole,
106 is an aluminum wiring, and 107 is a gate electrode and wiring layer made of polycrystalline silicon.

Next, a manufacturing method of this embodiment shown in FIG. 1 will be described.

First, a P-type silicon substrate 101 was heated to 100% in an oxidizing atmosphere.
Approximately 1,000
A silicon oxide film is formed, followed by a silicon nitride film of approximately 3,000 layers using the CVD method.

Next, unnecessary portions of the silicon nitride film are removed by photolithography, followed by oxidation at 1000° C. in an oxidizing atmosphere to form a silicon oxide film with a thickness of approximately 1 μm on the portions where the silicon nitride film was removed. Next, the silicon nitride film is removed to form an oxide film 103 for element isolation. Next, oxidation is performed at 1000° C. in an oxidizing atmosphere to form about 200 gate oxide films in the active region other than the element isolation oxide film 103. Next, a polycrystalline silicon film with a thickness of 500 mm was deposited using the CVD method.
After the 0-layer formation, unnecessary portions are removed by photolithography to form the gate electrode 107. Next, an N-type impurity, in this case phosphorus, is implanted at an energy of 80 KeV.

After ion implantation with a dose of 4 x 10"am-',
Annealing is performed at 00° C. to form an N-type impurity layer 102. Next, approximately 7,000 silicon oxide films are formed by CVD, and unnecessary portions of the silicon oxide films are removed by photolithography to form elongated contact holes 105. Next, aluminum is formed to a thickness of approximately 1 .mu.m by sputtering, and unnecessary portions of the aluminum are removed by photolithography to form aluminum wiring 106 extending across the short side of elongated contact hole 105.

For conventional contact holes as shown in Figures 2 (a) and (b), if the size is 0.6 μm in length and 0.6 μm in width, even if a reduction projection exposure device with a lens NA of -0.45 is used, the resist Although it is impossible to drill a hole in Figure 1 (
In this example as shown in a) and (b), if the contact hole size is 0.6 μm vertically and 5.0 μm horizontally, the lens NA
A hole in the resist can be opened by using a -0.45 reduction projection exposure apparatus.

In addition, if aluminum is sputtered in a conventional contact hole as shown in FIGS. 2(a) and 2(b) with a size of 0.8 μm vertically and 0.8 μm horizontally and a silicon oxide film 204 thickness of 7000, aluminum atoms Since it is difficult for aluminum to enter the contact hole, the thickness of the aluminum film in the contact hole ends up being less than 10% of the thickness of the aluminum film in the flat portion. On the other hand, in this embodiment shown in FIG. 1, the size of the contact hole is 0.8 μm5tffi5. 0
When aluminum is sputtered with the silicon oxide film 104 having a thickness of 7,000 μm, aluminum atoms from the long side direction of the contact hole easily enter the contact hole, and the aluminum film thickness at the center of the contact hole is flat. 40-50% of aluminum film thickness
Therefore, if the aluminum wiring is passed through the center of the contact hole, there will be no disconnection or poor contact.

In addition, if the size of the bottom of a conventional contact hole as shown in Fig. 2 is 0.8 μm vertically, 0.8 μm horizontally, and the thickness of the silicon oxide film 204 is 7000 mm, and the taper angle of the contact hole is 70'', then the contact hole The size of the upper part of is 1.3 μm vertically and 1.3 μm horizontally.Here, if the overlapping precision of the contact hole 205 and aluminum wiring 206 mask is 0.3 μm, the minimum dimension of the aluminum wiring width in Fig. 2 is 1. It becomes .9 μm.

On the other hand, in this embodiment shown in FIG. 1, the size of the bottom of the contact hole is 0.8 μm in length and 5.0 am in width.

The thickness of the silicon oxide film 104 is 7000A, the width of the N-type impurity layer 102 is 0.8 μm, and the overlay accuracy of the mask between the SN-type impurity layer 102 and the aluminum wiring 106 is 0.3.
When expressed as μm, the minimum dimension of the aluminum wiring width in FIG. 1 is 1.4 μm, and compared to the conventional example shown in FIG. 2, the aluminum wiring width can be made finer by 0.5 μm.

Furthermore, FIG. 3 shows the peripheral circuit section according to this embodiment, and FIG. 4 shows the peripheral circuit section according to the conventional example. In this embodiment, the contact area between the silicon substrate and the metal electrode in the contact hole is different from that of the conventional example. Since the contact resistance is relatively large, the contact resistance is reduced and the operating speed of the peripheral circuit section is increased, and as a result, the operating speed of the semiconductor memory device is also increased. Furthermore, in this embodiment, the width W of the active region within the contact hole in the peripheral circuit section is larger than that in the memory cell section. Even with miniaturization, a certain amount of contact area between the silicon substrate and the metal electrode within the contact hole of the peripheral circuit section can be secured. For example, if the length of the contact hole in the short side direction is 0.6 μm in Figures 1 and 3, and the width of the active region in Figure 1 is 0.6 μm, then the contact area between the silicon substrate and the metal electrode in the contact hole is 0.36μm
2, if the width W of the active region in FIG. 3 is 20 .mu.m, the contact area between the silicon substrate and the metal electrode in the contact hole is 12 .mu.m.sup.2, making it possible to keep the contact resistance low. As a result, the operating speed of the peripheral circuit section becomes faster, and the operating speed of the semiconductor memory device also becomes faster.

In this example, the LOCO3 method was used for element isolation, but the fifth
As shown in the figure, a trench isolation method may be used in which a trench is formed in a silicon substrate and then filled with an insulator to form an element isolation region 503. Further, in this embodiment, only two aluminum wires cross one elongated contact hole, but three or more aluminum wires may cross one elongated contact hole as shown in FIGS. 6(a) and 6(b). Furthermore, although aluminum was used for the wiring layer in this example, other high-melting point metals such as polycrystalline silicon, molybdenum, titanium, tungsten, etc.
Metals such as copper, iron, silver, and platinum may be used, and a wiring layer having a laminated structure in which these materials are stacked may be used.

Furthermore, in this embodiment, a static RAM cell is used as a memory cell, but this is different from a dynamic RAM, a mask R
It goes without saying that similar effects can be obtained when used in memory cells such as OM, EPROM, and EEPROM.

〔Effect of the invention〕

As described above, according to the present invention, if the contact hole formed in the memory cell portion of a semiconductor memory device is elongated and two or more wiring layers cross in the short side direction of the elongated contact hole, the contact hole and This makes it possible to miniaturize wiring layers and plays a major role in the miniaturization and higher integration of semiconductor memory devices. In addition, the aluminum wiring inside the contact hole has better coverage, which reduces the resistance of the connection between the silicon substrate and the aluminum wiring, increases the operating speed of the semiconductor storage device, and makes it resistant to electromigration. Increased reliability. Are there high-speed, high-quality semiconductor storage devices based on these factors? B! There is an effect that can be provided.

[Brief explanation of the drawing]

FIGS. 1(a) and 1(b) are a plan view and a sectional view showing an embodiment of a memory cell portion of a semiconductor memory device according to the present invention. FIGS. 2(a) and 2(b) are a plan view and a sectional view of a memory cell portion of a conventional semiconductor memory device. FIG. 3 is a plan view showing an embodiment of the peripheral circuit section of the semiconductor memory device according to the present invention. FIG. 4 is a plan view showing an embodiment of a peripheral circuit section of a conventional semiconductor memory device. FIG. 5 is a sectional view of a semiconductor memory device according to another embodiment of the present invention. FIGS. 6(a) and 6(b) are a plan view and a sectional view of a semiconductor memory device according to another embodiment of the present invention. 101.201.5 102.202.5 103.203.5 04.504.604 105.205.3 05・ ・ ・ ・ φ ・ Φ 106.206.3 06 ・ ・ ・ ・ ・ ・ ・ ・107. 207
．． 3 07 ・ ・ ・ ・ ・ ・ ・ 1.601 P-type silicon substrate 2.602 N-type impurity layer 3.603.104.2 Silicon oxide film 5.405.505.6 Contact hole 6.406.506.6 Aluminum electrode 7.407.507.6 Polycrystalline silicon electrode or more Calculation l C E) Concave Cb) Ao5 /'/7ri5 悌 ■ Me ■ Ca) Calculation (b) N/n05 and /) 7θS 憚Mero 0 ( vinegar

Claims (1)

[Claims] In a semiconductor memory device comprising a memory cell portion formed in a semiconductor substrate and a peripheral circuit portion, a contact hole formed in the memory cell portion and the peripheral circuit portion is elongated, and a contact hole formed in the memory cell portion and the peripheral circuit portion is elongated. The formed wiring layer traverses the short side direction of the elongated contact hole,
The wiring layer covers an active region formed in the memory cell portion and the peripheral circuit portion within the contact hole,
A semiconductor memory device characterized in that the width of the active region within the contact hole is wider in the peripheral circuit section than in the memory cell section.