JPH02159041A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH02159041A JPH02159041A JP63314025A JP31402588A JPH02159041A JP H02159041 A JPH02159041 A JP H02159041A JP 63314025 A JP63314025 A JP 63314025A JP 31402588 A JP31402588 A JP 31402588A JP H02159041 A JPH02159041 A JP H02159041A
- Authority
- JP
- Japan
- Prior art keywords
- film
- insulating film
- forming
- gate
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- Electrodes Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、高性能な半導体装置の製造方法に関するもの
である。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a method of manufacturing a high performance semiconductor device.
従来の技術
従来のMO3型半導体装置のソース・ドレインの形成方
法では、第3図に示すように、半導体基板21にフィー
ルド酸化膜22.ゲート絶縁膜23および多結晶硅素膜
などのゲート電極パターン24を形成した後、低濃度不
純物拡散層を形成し、(同図(A))、次に前記多結晶
硅素膜パターン側壁に絶縁膜25を形成し、前記側壁絶
縁膜をマスクとして、前記半導体基板に高濃度不純物層
26をイオン注入法により形成し、ソース・ドレインと
していた(同図(B)〉。2. Description of the Related Art In the conventional method for forming sources and drains of MO3 type semiconductor devices, as shown in FIG. 3, a field oxide film 22 . After forming a gate insulating film 23 and a gate electrode pattern 24 such as a polycrystalline silicon film, a low concentration impurity diffusion layer is formed (FIG. 2(A)), and then an insulating film 25 is formed on the sidewalls of the polycrystalline silicon film pattern. , and using the sidewall insulating film as a mask, a highly concentrated impurity layer 26 was formed on the semiconductor substrate by ion implantation to serve as a source/drain (FIG. 3(B)).
発明が解決しようとする課題
上記従来の方法では、高濃度イオン注入時に前記ゲート
電極パターンに電荷が蓄積され、基板との間に高電圧が
印加され、ゲート絶縁膜が破壊されるという問題があっ
た。Problems to be Solved by the Invention The conventional method described above has the problem that charge is accumulated in the gate electrode pattern during high-concentration ion implantation, and a high voltage is applied between the gate electrode pattern and the substrate, destroying the gate insulating film. Ta.
課題を解決するための手段
本発明は、上記問題点を解決するため、ソース・ドレイ
ン上の絶縁膜厚を除去し、又はゲート絶縁膜厚より薄く
し、かつゲート絶縁膜上にも絶縁膜を形成した後、全面
に導電体膜を薄(形成し、高濃度不純物層をイオン注入
法により形成してソース・ドレイン層を形成するもので
ある。Means for Solving the Problems In order to solve the above problems, the present invention removes the thickness of the insulating film on the source/drain or makes it thinner than the gate insulating film, and also forms an insulating film on the gate insulating film. After the formation, a thin conductive film is formed over the entire surface, and a highly concentrated impurity layer is formed by ion implantation to form source/drain layers.
作 用
本発明の方法によれば、高濃度不純物層形成時に生ずる
導電体膜の電荷を全てソース・ドレイン領域に直接、又
は、ソース・ドレイン領域上の薄い絶縁膜を介して、基
板にリークさせることができるため、従来例のようにゲ
ート絶縁膜を破壊させることがな(、高性能のMO8型
電界効果型半導体装置を製造することができる。Effect: According to the method of the present invention, all of the charges in the conductor film generated during the formation of the highly concentrated impurity layer are leaked to the substrate directly to the source/drain region or via a thin insulating film on the source/drain region. Therefore, a high-performance MO8 type field effect semiconductor device can be manufactured without destroying the gate insulating film as in the conventional example.
実 施 例 第1図に従って本発明の一実施例を説明する。Example An embodiment of the present invention will be described with reference to FIG.
−導電型半導体基板1上に、選択的にフィールド酸化膜
2およびゲート酸化膜3を形成した後、全面にゲート電
極材料4、例えば不純物含有多結晶硅素膜を形成する。- After selectively forming a field oxide film 2 and a gate oxide film 3 on a conductive semiconductor substrate 1, a gate electrode material 4, such as an impurity-containing polycrystalline silicon film, is formed on the entire surface.
次に、前記多結晶硅素膜4上に前記ゲート酸化膜より厚
い二酸・化硅素膜5を形成(同図(A))した後、前記
多結晶硅素膜4および二酸化硅素膜5に所定のゲート電
極パターン6を形成し、前記半導体基板に低濃度不純物
層7を形成する(同図(B))。全面に絶縁膜を形成し
た後エッチバック法により前記ゲート電極パターン側壁
に前記絶縁膜8を形成する。このときエッチバック時間
を前記絶縁膜8の膜厚分食刻する時間より長(食刻し、
前記多結晶硅素膜4と側壁絶縁膜8以外に露出したゲー
ト酸化膜を薄(食刻する(同図(C))。あるいは全て
食刻し、半導体基板を露出する。次に全面に導電体膜9
、例えば不純物含有多結晶硅素膜を形成した後、高濃度
不純物を前記半導体基板にイオン注入し、高濃度ソース
・ドレイン層10を形成する(同図(D))。次に前記
導体膜9をすべて除去したのち層間膜11および金属配
線層12を形成して半導体装置を形成する(同図(E)
)。Next, after forming a dioxide/silicon oxide film 5 thicker than the gate oxide film on the polycrystalline silicon film 4 (see FIG. A gate electrode pattern 6 is formed, and a low concentration impurity layer 7 is formed on the semiconductor substrate (FIG. 3(B)). After forming an insulating film over the entire surface, the insulating film 8 is formed on the side walls of the gate electrode pattern by an etch-back method. At this time, the etch-back time is longer than the etching time for the film thickness of the insulating film 8 (etching,
The gate oxide film exposed except for the polycrystalline silicon film 4 and the sidewall insulating film 8 is thinly etched (FIG. (C)). Alternatively, the entire gate oxide film is etched to expose the semiconductor substrate. Next, a conductor is deposited on the entire surface. membrane 9
For example, after forming an impurity-containing polycrystalline silicon film, high concentration impurities are ion-implanted into the semiconductor substrate to form a high concentration source/drain layer 10 (FIG. 3(D)). Next, after completely removing the conductive film 9, an interlayer film 11 and a metal wiring layer 12 are formed to form a semiconductor device (see FIG.
).
なお、上記実施例でゲート電極側壁に絶縁膜を形成(第
1図(C))した後、ソース・ドレイン上のゲート酸化
膜13をすべて除去した後、導電体膜9を形成して高濃
度ソース・ドレイン層を形成しても良い。このときは、
第2図に示すように、前記導体1摸をすべて除去せずに
選択的に残しておき、ソース・ドレインからの引出し配
線14として用いても良い。In the above embodiment, after forming an insulating film on the sidewalls of the gate electrode (FIG. 1(C)) and removing all the gate oxide film 13 on the source/drain, a conductive film 9 is formed to form a high-concentration film. A source/drain layer may also be formed. At this time,
As shown in FIG. 2, the conductor 1 may be selectively left without being completely removed and used as the lead wiring 14 from the source/drain.
発明の効果
本発明の方法によれば、ソース・ドレインの高濃度不純
物層形成時に全面に導電体膜を形成し、かつゲート酸化
膜より薄い酸化膜を介して、あるいは直接ソース・ドレ
イン領域の半導体基板に接しているため、イオン注入時
に表面に誘起される電荷はすべて、ソース・ドレイン領
域に流れ、ゲート酸化膜が破壊されることがな(、特性
の良好な半導体装置を形成することができる。Effects of the Invention According to the method of the present invention, a conductive film is formed on the entire surface when forming a high concentration impurity layer in the source/drain, and the conductive film is formed on the entire surface of the semiconductor in the source/drain region through an oxide film thinner than the gate oxide film or directly. Because it is in contact with the substrate, all the charges induced on the surface during ion implantation flow to the source/drain region, preventing the gate oxide film from being destroyed (which makes it possible to form a semiconductor device with good characteristics). .
第1図は本発明の一実施例を説明するための工程断面図
、第2図は本発明の他の実施例を説明す膜。
代理人の氏名 弁理士 粟野重孝 はか1名1・・・・
・・半導体基板、3・・・・・・ゲート絶縁膜、4・・
・・・・ゲート電極、5,8・・・・・・絶縁膜、9・
・・・・・導体第
図FIG. 1 is a process sectional view for explaining one embodiment of the present invention, and FIG. 2 is a film for explaining another embodiment of the present invention. Name of agent: Patent attorney Shigetaka Awano Haka 1 person 1...
...Semiconductor substrate, 3...Gate insulating film, 4...
...Gate electrode, 5, 8... Insulating film, 9.
・・・Conductor diagram
Claims (2)
て、ゲート絶縁膜より薄い絶縁膜を介して半導体基板全
面に導体膜を形成する工程と、前記導体膜上から前記半
導体基板にイオン注入法により不純物を注入してソース
・ドレインを形成する工程と、前記導体膜を除去する工
程とを含むことを特徴とする半導体装置の製造方法。(1) In the manufacturing process of a MOS type field effect semiconductor device, there is a step of forming a conductive film on the entire surface of the semiconductor substrate through an insulating film thinner than the gate insulating film, and an ion implantation method into the semiconductor substrate from above the conductive film. A method of manufacturing a semiconductor device, comprising the steps of forming a source/drain by implanting impurities, and removing the conductor film.
てゲート電極と絶縁膜を介し、かつゲート領域以外で半
導体基板と接した導体膜を形成する工程と、導体膜を通
して半導体基板にイオン注入法により不純物を導入する
工程とを含むことを特徴とする半導体装置の製造方法。(2) In the manufacturing process of a MOS field effect semiconductor device, a process of forming a conductor film in contact with the semiconductor substrate through the gate electrode and the insulating film and in areas other than the gate region, and an ion implantation method into the semiconductor substrate through the conductor film. A method for manufacturing a semiconductor device, comprising the step of introducing an impurity.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63314025A JPH02159041A (en) | 1988-12-13 | 1988-12-13 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63314025A JPH02159041A (en) | 1988-12-13 | 1988-12-13 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02159041A true JPH02159041A (en) | 1990-06-19 |
Family
ID=18048304
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63314025A Pending JPH02159041A (en) | 1988-12-13 | 1988-12-13 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02159041A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06310731A (en) * | 1990-12-21 | 1994-11-04 | Samsung Electron Co Ltd | Nonvolatile semiconductor memory cell and manufacturing method thereof |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57202783A (en) * | 1981-06-05 | 1982-12-11 | Mitsubishi Electric Corp | Manufacture of insulated gate type field-effect transistor |
| JPS63114129A (en) * | 1986-10-31 | 1988-05-19 | Sony Corp | Manufacture of semiconductor device |
-
1988
- 1988-12-13 JP JP63314025A patent/JPH02159041A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57202783A (en) * | 1981-06-05 | 1982-12-11 | Mitsubishi Electric Corp | Manufacture of insulated gate type field-effect transistor |
| JPS63114129A (en) * | 1986-10-31 | 1988-05-19 | Sony Corp | Manufacture of semiconductor device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06310731A (en) * | 1990-12-21 | 1994-11-04 | Samsung Electron Co Ltd | Nonvolatile semiconductor memory cell and manufacturing method thereof |
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