JPH02162810A - Bias circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a bias circuit equipped with a temperature compensation circuit.

[Conventional technology]

FIG. 2 is a connection diagram showing a conventional bias circuit. In the figure, (old) is a zener diode, (El) and (R
3) is the gate bias terminal, (R2) and (R4) are the drain bias terminals, and (R5) and (R6) are the power supply terminals.

(R7) is a ground terminal, and (old) to (R7) are resistors.

(RTI) is a posistor, and (TRI) and (TR2) are field effect transistors.

A conventional bias circuit can be explained as follows.

A negative voltage is supplied to the first field effect transistor (TRI) from the gate bias terminal (El).

The gate bias terminal (El) is connected to the point P' shown in Fig. 2.
If the voltage at is Vp', then the first resistance (
A value multiplied by the voltage Vp' is added to the ratio of the resistance values of R1).

Similarly, the gate bias terminal (R3) of the second field effect transistor (TR2) has a fourth resistance (R
A value obtained by multiplying the resistance value ratio in 4) by the voltage Vp' is added.

This voltage vp' is the Zener diode (old) shown in Figure 2.
It is determined by the zener voltage, which is a characteristic of

On the other hand, the drain bias terminal (R2) of the first field effect transistor (TRI) is connected to the positive power supply terminal (R2).
A voltage obtained by subtracting the voltage drop of the third resistor (R3) from the voltage of 6) is applied. Similarly, the second field effect transistor (TR2) is supplied with a positive voltage from the positive power supply terminal (R6) through the sixth resistor (R6) and the drain terminal (R4). Note that the terminal (El) is a ground terminal.

[Problem to be solved by the invention]

In the conventional bias circuit as described above, when the constant of the posistor for temperature compensation or the number of stages of the field effect transistors is changed, the bias circuit of the first field effect transistor (TRII) and the second field effect transistor (TR2) changes. This invention was made to solve these problems, and it is possible to adjust the bias circuit by changing the constant of the POSISTOR or changing the number of stages of the field effect transistor. adjustment.

The aim is to keep it to a minimum.

[Means to solve the problem]

In the bias circuit according to the present invention, a resistor is inserted electrically in parallel to the gate bias circuit of a field effect transistor.

[For production]

The bias circuit according to the present invention can adjust the combined resistance value of the gate bias circuit by using a resistor electrically inserted in parallel with the gate bias circuit of the field effect transistor. It acts to minimize the adjustment of the bias circuit due to the change.

〔Example〕

FIG. 1 is a connection diagram showing an embodiment of the present invention.

In the figure, (DI) is a zener diode, (El
) and (R3) are gate bias terminals, (R2) and (
R4) is the drain bias terminal, (R5) and (R6
) is the terminal for Ti source.

(El) is the ground terminal, (R1) to (R8) are resistors.

(RTI) is a posistor, and (TI) and (TR2) are field effect transistors.

Next, an example will be described. A first field effect transistor (TRI) and a second field effect transistor (TR
2) When adjusting the voltage applied to the gate bias terminals (El) and (R3), the gate side bias resistance,
In other words, the first resistor (old), the second resistor (R2) and the fourth resistor
XPJ is adjusted so that the combined resistances RrB and Rr4B of the resistance (R4) and the fifth resistance are constant.

The above-mentioned combined resistance Rr12 and Rrts and the eighth resistance (R8
) is the combined resistance of the zener diode (D
The terminal voltage of I) is Vz, and the resistance of the POSISTOR (RTI) is R.
Assuming r5, the voltage Vp at two points P is expressed by the following equation.

R" ■p = Vz ・ ・ ・ ・
(1) Rrtl+Rr In the above equation, the 9 combined resistance value Rr and the Zener voltage Vz are constant, so when the environmental temperature changes, the voltage Vp is controlled in relation to the temperature change of the resistance value Rrtl.

Furthermore, if the terminal voltages of the gate bias terminals (El) and (R3) are vgl and Vga, respectively, then the voltage v
It is expressed by the following equation using p.

In the above formula, p RIR4*RrL! Since and Rr4B are constant, when the environmental temperature changes, the voltage vp is controlled in relation to the temperature change.

Here, in the above bias circuit, when the constant of the temperature compensation posistor is changed, the gate bias terminal (El) and (R3) are connected before and after the change of the posistor constant.
It is necessary to make the voltages the same. In this circuit, after changing the constant of the POSISTOR, the eighth resistor (R8) is used to adjust the voltage Vp to the same voltage as before the change.
2) Vg+ before and after changing the posistor constant using equation 2 (3)
and vg2 become equal.

Also, when changing the number of stages of field effect transistors, it is necessary to make V equal to 1 and Vgz before and after the change, but the eighth resistor (R8) must be adjusted so that the two combined resistances Rr remain constant. By simply doing this, Vp does not change before and after changing the number of Ti field effect transistor stages, so Vg+ and Vgz do not change in terms of song.

〔Effect of the invention〕

As explained above, in this invention, the combined resistance value of the gate bias circuit of a field effect transistor is

Since it is configured so that it can be adjusted with a resistor inserted in parallel to the gate bias circuit, if the constant of the POSISTOR or the number of stages of the field effect transistor is changed, it is possible to re-adjust the 7A with only one resistor. .

[Brief explanation of the drawing]

FIG. 1 is a connection diagram showing an embodiment of a bias circuit according to the present invention, and FIG. 2 is a connection diagram showing a conventional bias circuit. In the figure, (old) is a zener diode, (El) to (
R7) is a terminal, (old) to (R8) are resistors, (RTI
) is Posista. (TRI) and (TR2) are field effect transistors. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

[Claims] a first field effect transistor; a gate bias terminal connected to the gate terminal of the first field effect transistor; and a first resistor, one of which is connected to the gate bias terminal and the other of which is grounded. , a second resistor having one end connected to the gate bias terminal, a drain bias terminal connected to the drain terminal of the first field effect transistor, and a third resistor having one end connected to the drain bias terminal. A first basic bias circuit consisting of a circuit similar to the first basic bias circuit,
A second basic bias provided with a gate bias terminal, a fourth resistor, a fifth resistor, a drain bias terminal, and a sixth resistor, the other of the second resistors of the first basic bias circuit, and the second basic bias circuit. an eighth resistor, one of which is connected to the other of the fifth resistor, and the other of which is grounded;
a POSISTOR having one end connected to one of the eighth resistors, a Zener diode having one end connected to the other end of the POSISTOR and the other terminal thereof being grounded, and a seventh resistor connected to the other end of the POSISTOR. and a negative power supply terminal connected to the seventh resistor, and a positive power supply terminal connected to the other of the third resistor of the first basic bias circuit and the other of the sixth resistor of the second basic bias circuit. and a bias circuit with a ground terminal.