JPH02168774A - Phase locked loop device - Google Patents

Abstract

PURPOSE:To obtain a clock pulse synchronously with a horizontal synchronizing signal in a video signal through simple circuit constitution by providing a differential detection circuit detecting a difference between a pedestal level obtained from a 1st sample-and-hold circuit and a level obtained from a 2nd sample-and- hold circuit and feeding back the difference to an oscillator generating the clock pulse. CONSTITUTION:A tri-state synchronizing High vision video signal 53 inputted from an input terminal 51 to a buffer amplifier 52 is subjected to impedance conversion and becomes a low impedance video signal 54 and fed respectively to the 1st sample-and-hold circuit 55, the 2nd sample-and-hold circuit 68 and a synchronizing separator circuit 56. The synchronizing separator circuit 56 is similar to a circuit extracting a synchronizing signal from a video signal, extracts a negative synchronizing signal 57 from the low impedance video signal 54 inputted thereto and gives the signal to a pulse generating circuit 58. The sample-and-hold circuit 55 uses a back porch sample pulse 59 to extract a pedestal level 60 from the low impedance video signal 54 and gives it to one input of a difference detection circuit 61.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a video device, and more particularly to a phase lock-loose device that generates tough lock pulses in synchronization with a horizontal synchronizing signal of a quantized three-level synchronous video signal. It is something.

[Conventional technology]

Figure 2 is a diagram illustrating a three-level synchronous video signal. ),
FIG. 83 is a block diagram showing a conventional phase-locked loop (hereinafter referred to as PLL) device.

The ternary synchronous video signal 11 shown in FIG. 2 is used as a high-definition video signal.

This three-level synchronous video signal 11 is obtained by adding a positive polarity synchronizing signal 13 immediately after a normal negative polarity synchronizing signal 12. The reference edge 14 is given as the point at which the ternary opening signal exceeds the bedenutal level 15 when it rises from negative to positive. Note that the levels of each part of this video signal 11 are distributed as shown.

Next, a conventional PLI and device will be explained with reference to FIG.

In FIG. 3, a three-level synchronous type Ivision video signal 221-1i input from the input terminal 21, a low impedance video signal 24 through the entire buffer amplifier 23,
becomes. This low impedance video signal 24 is passed to the sync separation circuit 25. Sample and hold circuit 26. It is supplied to comparator 2T. The synchronization separation circuit 25 extracts a negative polarity synchronization signal 28 from this low impedance video signal 24 and sends it to a pulse generation circuit 29 and a gate circuit 30.

From this negative polarity synchronization signal 28, the pulse generation circuit 29 generates
A bank pouch sample pulse 29A located at the rear of the positive polarity synchronization signal 13 shown in FIG. 2 is generated and sent to the sample hold circuit 26. Upon receiving this, the sample and hold circuit 26 captures the back porch potential of the low impedance video signal using the back porch sample pulse 29A, and provides the pedestal level 15 shown in FIG. Then, send it to this hetestal level 15'l & coparator 21. The comparator 27 slices the low impedance video signal 24 based on the pedestal level 15 and provides information 31 regarding the reference phase of the input ternary synchronous high-definition video signal 22 to the gate circuit 30.

The gate circuit 30 gates information 31 regarding the reference phase, which is the output of the comparator 27, using the synchronization signal 28 from the synchronization separation circuit 25, extracts only the edge 14 of the reference phase, and selects one of the edges of the phase comparator 33. give to input.

A horizontal synchronizing pulse 35 output from the counter circuit 34 is input to another input of the phase comparator 33. This horizontal synchronization pulse 35 is obtained by counting down the clock pulse 37, which is the output of the oscillator 36, by the counter circuit 34 to the same frequency as the horizontal synchronization frequency.

The output 38 of the phase comparator 33 is fed back to the oscillator 36 and thus clock pulse 3γ and horizontal synchronization pulse 3
5 is synchronized with a horizontal synchronizing signal in the ternary synchronized high-definition video signal 22. Note that these clock pulses 3
1 and the horizontal synchronization bulk 35 are sent out from output terminals 39 and 40.

[Problem to be solved by the invention]

However, the conventional PLL device described above has the following drawbacks. That is, the comparator 27 is required to obtain the edge 14 of the reference phase, and therefore synchronous separation is performed twice. Furthermore, a gate circuit 30 and a phase comparator 3
3 is also required, and there is a problem that the device becomes large.

SUMMARY OF THE INVENTION An object of the present invention is to provide a PLL device that eliminates the need for additional circuitry by utilizing the properties of a three-level synchronous high-definition video signal.

[Failure to solve the problem]

In order to achieve the above object, the PLL device of the present invention includes a sync separation circuit that separates a sync signal from an input ternary synchronous high-definition video signal, and a back porch sample pulse that generates a back porch sample pulse from the separated sync signal. A pulse generation circuit, a first sample and hold circuit that extracts the pedestal potential of the three-level synchronous non-vision video signal using the back porch sample pulse, and a horizontal synchronization signal of the three-level synchronous non-vision video signal. an oscillator that generates a clock pulse synchronized with the clock pulse, a counter circuit that counts down this clock pulse to generate a horizontal synchronization pulse, and a second sample that samples and holds the three-level synchronous no-vision video signal using the horizontal synchronization pulse. It includes a hold circuit and a difference detection circuit that detects the difference between the pedestal potential obtained by the first sample and hold circuit and the potential obtained by the second sample and hold circuit and feeds it back to an oscillator that generates a clock pulse. It is something.

[Effect]

Therefore, according to the present invention, a clock pulse synchronized with a horizontal synchronization signal in a video signal can be obtained with a simple circuit configuration by obtaining a reference phase edge using a three-level synchronized non-vision video signal. .

〔Example〕

Hereinafter, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a PLL device according to the present invention.

In FIG. 1, from the input terminal 51 to the buffer amplifier 52
The three-level synchronous high-definition video signal 53 inputted to the circuit 53 is impedance-converted and converted into a low-impedance video signal 54, which is then input to the first sample-and-hold circuit 55. Second
Sample and hold circuit 68. The signals are sent to the synchronization separation circuit 56, respectively. This synchronization separation circuit 56 is of the same type as one that extracts a synchronization signal from a normal video signal, and extracts a negative polarity synchronization signal 5r from the input low impedance video signal 54 and sends it to a pulse generation circuit 58. .

Upon receiving this, the pulse generation circuit 58 generates a pulse (back porch sample pulse 59) indicating the phase before the start of the video immediately after synchronization from this negative polarity synchronization signal 5γ, and sends it to the first sample halt circuit 55. do. This sample hold circuit 55 has a back porch sample pulse 59
The pedestal potential 60 is taken out from the low impedance video signal 54 and applied to one input of the difference detection circuit 61.

On the other hand, the oscillator 62 generates a target clock pulse 63 and sends it to the counter circuit 64 and the clock pulse output terminal 65. This counter circuit 64 counts down the input clock pulse 63 and sends a horizontal synchronizing pulse 66 to a second sample hold circuit 68 and a horizontal synchronizing pulse output terminal 69. Further, the second sample and hold circuit 68 extracts an arbitrary phase of the low impedance video signal 54 using the horizontal synchronizing pulse 66 and sends it to the difference detection circuit 61 . Thereby, the difference detection circuit 61 feeds back the difference between the pedestal potential 60 and the potential extracted by the horizontal synchronizing pulse 66 to the oscillator 62. Here, the oscillator 62. Counter circuit 64
．． Second sample and hold circuit 68. Difference detection circuit 61
The feedback loop, which is constructed in many ways, is referenced to the pedestal potential 60 and is connected to the low impedance video signal 54.
The horizontal synchronization pulse 66 coincides with the reference phase because the movement above and below this point is limited to the vicinity of the reference phase of horizontal synchronization.

〔Effect of the invention〕

As explained above, the PLL device of the present invention utilizes the properties of a ternary synchronized high-definition video signal to obtain the edge of the reference phase, thereby performing double synchronization separation as in the conventional method. A clock pulse synchronized with a horizontal synchronizing signal in a video signal can be obtained with a simple circuit configuration without using any circuit. Therefore, compared to the conventional method, it is possible to reduce the amount of hardware, and also to save space and reduce costs.

[Brief explanation of the drawing]

Figure 1 shows a phase-locked loop (PLL) according to the present invention.
FIG. 2 is a block diagram showing one embodiment of the device; FIG. 2 is a diagram showing an example of a normal three-value synchronous non-vision video signal;
The figure shows an example of a conventional phase lock loop device. 52...me buffer amplifier 7', 55...first sample hold circuit, 56, fist Luro synchronization separation circuit, 58
...Fist/pulse generation circuit, 61...Difference detection circuit,
62...-oscillator, 64... counter circuit, 68
・Contest・Second sample and hold circuit.

Claims (1)

[Claims] A sync separation circuit that separates a sync signal from an input ternary synchronous high-definition video signal, a pulse generation circuit that generates a back porch sample pulse from the separated sync signal, and a sync separation circuit that generates a back porch sample pulse from the separated sync signal; a first sample and hold circuit for extracting the pedestal potential of the three-level synchronized high-definition video signal; an oscillator that generates a clock pulse synchronized with the horizontal synchronization signal of the three-level synchronized high-definition video signal; and a horizontal synchronization pulse by counting down the clock pulse. a second sample-and-hold circuit that samples and holds the three-level synchronous high-definition video signal using the horizontal synchronizing pulse; and a pedestal potential obtained by the first sample-and-hold circuit and a second sample-and-hold circuit. A phase-locked loop device comprising: a difference detection circuit that detects a difference in potential obtained by the circuit and feeds it back to an oscillator that generates the clock pulse.