JPH02185060A - Lead frame for semiconductor device - Google Patents
Lead frame for semiconductor deviceInfo
- Publication number
- JPH02185060A JPH02185060A JP571489A JP571489A JPH02185060A JP H02185060 A JPH02185060 A JP H02185060A JP 571489 A JP571489 A JP 571489A JP 571489 A JP571489 A JP 571489A JP H02185060 A JPH02185060 A JP H02185060A
- Authority
- JP
- Japan
- Prior art keywords
- copper
- lead frame
- silver
- resin
- semiconductor element
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、半導体am回路(IC)チップなどを搭載
する半導体用リードフレームの構造に関するものである
。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to the structure of a semiconductor lead frame on which a semiconductor am circuit (IC) chip or the like is mounted.
この種の半導体装置用リードフレームは、第3図に示す
ように、所定数に区分されたリードフレーム素体として
のリードフレーム枠5と、このリードフレーム枠5の中
央部分に支持された半導体素子載置部6と、この半導体
素子載置部6に搭載される半導体素子(図示せず)の各
々の電極端子をワイヤ線を介して外部へ導出するための
外部接続用の複数のリード7を具備している。そしてこ
のリード7は、半導体素子載置部6の周辺にそれぞれ所
定の間隔をもって放射状に配設された内部リード部8と
、該内部リード部8の他端側に互いに連接して平行に配
設された外部リード部9により構成されている。また、
前記リード7の中間部分には、それらリードの離間位置
を安定に保つとともに、樹脂封止の際に当該樹脂が外部
へ漏出するのを防止するためにタイバーIOが一体に連
結されている。なお、第3図中、点線で囲まれた領域1
1は半導体封止用樹脂領域を示し、この樹脂領域11内
に含まれる半導体素子載置部6の一部をなすリード片6
aも通常内部リード部と称している。As shown in FIG. 3, this type of lead frame for a semiconductor device includes a lead frame frame 5 as a lead frame body divided into a predetermined number of parts, and a semiconductor element supported in the center part of this lead frame frame 5. A mounting part 6 and a plurality of external connection leads 7 for leading out each electrode terminal of a semiconductor element (not shown) mounted on the semiconductor element mounting part 6 to the outside via a wire line. Equipped with The leads 7 are connected to an internal lead part 8 which is arranged radially around the semiconductor element mounting part 6 at a predetermined interval, and which are arranged parallel to each other on the other end side of the internal lead part 8. The external lead portion 9 is made up of an external lead portion 9. Also,
A tie bar IO is integrally connected to the intermediate portion of the leads 7 in order to maintain the stable separation position of the leads and to prevent the resin from leaking to the outside during resin sealing. In addition, in Figure 3, area 1 surrounded by dotted lines
Reference numeral 1 indicates a resin region for semiconductor sealing, and a lead piece 6 forming a part of the semiconductor element mounting portion 6 included in this resin region 11
A is also usually referred to as an internal lead portion.
次に動作について説明する。半導体素子載置部6に半導
体素子(図示せず)をチップボンディングした後、該半
導体素子の各々の電極端子とり−ド7の内部リード部8
とのワイヤボンディングを行う0次いで通常樹脂封止工
程にて、半導体素子およびワイヤ線を含む内部リード部
8を樹脂封止した後、フレーム枠5およびタイバー10
を切離すことにより、樹脂封止形半導体装置が完成され
る。Next, the operation will be explained. After chip bonding a semiconductor element (not shown) to the semiconductor element mounting part 6, the internal lead part 8 of each electrode terminal lead 7 of the semiconductor element is bonded.
0 Next, in a normal resin sealing process, the internal lead part 8 including the semiconductor element and the wire wire is sealed with resin, and then the frame frame 5 and the tie bar 10 are sealed.
By separating, a resin-sealed semiconductor device is completed.
そして、近年このようなリードフレームにおいて、銅又
は銅合金系リードフレーム素材に直接、あるいは銅めっ
き皮膜を介してボンディングを行う技術が開発されてい
る。In recent years, techniques have been developed for bonding such lead frames directly to the copper or copper alloy lead frame material or via a copper plating film.
上記のような半導体装置用リードフレームにおいては、
チップボンディング以降の組立工程において受ける熱ス
トレスにより、銅表面に酸化皮膜が形成されて、ワイヤ
ボンディングが行えず、また、銅酸化皮膜は、銅母材と
の密着力が弱いために銅母材〜銅酸化皮膜間で剥離現象
が発生し、半導体装置の信頼性を低下させるという問題
点かあった。In the lead frame for semiconductor devices as described above,
Due to the heat stress received during the assembly process after chip bonding, an oxide film is formed on the copper surface, making wire bonding impossible.Also, the copper oxide film has weak adhesion to the copper base material, so There was a problem in that a peeling phenomenon occurred between the copper oxide films, reducing the reliability of the semiconductor device.
また、銅酸化皮膜の生成を抑制する方法として、特開昭
62−163353号に示されるように銅表面に銀皮膜
を形成する方法があるが、銀は樹脂との密着力が弱くて
樹脂を用いた場合のチップボンディングが行えず、また
、樹脂封止工程にて、リードフレームと樹脂との密着力
が弱く、半導体装置の信頼性を低下させるという問題点
があった。In addition, as a method for suppressing the formation of a copper oxide film, there is a method of forming a silver film on the copper surface as shown in JP-A No. 62-163353, but silver has a weak adhesion to resin and the resin When used, chip bonding cannot be performed, and the adhesion between the lead frame and the resin is weak in the resin sealing process, resulting in lower reliability of the semiconductor device.
この発明は上記のような問題点を解消するためになされ
たもので、銅表面の酸化皮膜の生成を抑制するとともに
、樹脂との密着力が高く、信頼度の高い半導体装置を得
ることのできる半導体装置用リードフレームを提供する
ことを目的とする。This invention was made in order to solve the above-mentioned problems, and it is possible to suppress the formation of an oxide film on the copper surface, and to obtain a highly reliable semiconductor device with high adhesion to resin. The purpose of the present invention is to provide a lead frame for semiconductor devices.
この発明に係る半導体装置用リードフレームは、銅また
は銅合金系のリードフレーム、あるいは表面に銅めっき
加工が施されたリードフレームであって、少なくとも半
導体素子を搭載する半導体装置部と、この半導体素子載
置部の周囲にそれぞれ所定の間隔をもって配設された複
数のリードとをリードフレーム枠に一体に連結してなる
ものにおいて、該リードフレームの表面に薄い銀皮膜を
形成して加熱することにより銅及び銀の相互拡散層を形
成したことを特徴とするものである。The lead frame for a semiconductor device according to the present invention is a lead frame made of copper or a copper alloy, or a lead frame whose surface is plated with copper, and includes at least a semiconductor device portion on which a semiconductor element is mounted, and a lead frame that includes a semiconductor device part on which a semiconductor element is mounted, and a lead frame that includes a semiconductor element. In a product in which a plurality of leads arranged at predetermined intervals around a mounting part are integrally connected to a lead frame frame, a thin silver film is formed on the surface of the lead frame and heated. It is characterized by forming a mutual diffusion layer of copper and silver.
この発明においては、銅表面に銀皮膜を形成することに
より銅酸化皮膜の生成を抑制するとともに、加熱による
銅及び銀の相互拡散層を設けることにより、チップボン
ディング用樹脂及び封止用樹脂との高い密着力を得るこ
とが出来る。In this invention, the formation of a copper oxide film is suppressed by forming a silver film on the copper surface, and by providing a mutual diffusion layer of copper and silver by heating, it is possible to prevent the formation of a copper oxide film by forming a silver film on the copper surface. High adhesion can be obtained.
〔実施例〕 ′ 以下この発明の一実施例を図について説明する。〔Example〕 ' An embodiment of the present invention will be described below with reference to the drawings.
第1図は、本発明の一実施例による半導体リードフレー
ムの製造工程を示す概略断面フロー図である。FIG. 1 is a schematic cross-sectional flow diagram showing the manufacturing process of a semiconductor lead frame according to an embodiment of the present invention.
この実施例による半導体装置用リードフレームは、まず
銅合金系からなるリードフレーム素材1(第1図a)の
表面上に銅めっき皮膜2を形成する(第11Mb>、次
いでその上から0.1μm以下の銀皮膜3を形成しく第
1図c)、その後加熱により銅及び銀の相互拡散層4を
形成する(第1図d)ものである。In the lead frame for a semiconductor device according to this embodiment, a copper plating film 2 is first formed on the surface of a lead frame material 1 (FIG. 1a) made of a copper alloy (11 Mb>, and then 0.1 μm from above). The following silver film 3 is formed (FIG. 1c), and then a mutual diffusion layer 4 of copper and silver is formed by heating (FIG. 1d).
また第2図は、本実施例によるリードフレーム表面に銅
及び銀の相互拡散層を具備したリードフレーム並びに従
来の技術による銀皮膜を形成しない銅めっきのみのリー
ドフレーム及び銅表面に銀皮膜を形成しただけのリード
フレームに対する樹脂との密着強度を比較した図である
。Figure 2 also shows a lead frame with a mutual diffusion layer of copper and silver on the surface of the lead frame according to this embodiment, a lead frame with only copper plating without forming a silver film according to the conventional technology, and a lead frame with a silver film on the copper surface. FIG. 3 is a diagram comparing the adhesion strength between resin and a lead frame that has only been used.
なお、第2図において、本実施例により得られる銅及び
銀の相互拡散層を設けたリードフレームの密着強度を1
00としたときの割合を示している。In addition, in FIG. 2, the adhesion strength of the lead frame provided with the mutual diffusion layer of copper and silver obtained in this example is 1.
The percentage is shown when it is set to 00.
すなわち第2図より、リードフレーム表面に銅及び銀の
相互拡散層を設けることにより、銅酸化皮膜の生成しに
くくかつ樹脂との密着力の強いことがわかる。That is, from FIG. 2, it can be seen that by providing a mutual diffusion layer of copper and silver on the surface of the lead frame, it is difficult to form a copper oxide film and the adhesion to the resin is strong.
以上のようにこの発明によれば、リードフレーム表面に
銅及び銀の相互拡散層を設けることにより、銅酸化皮膜
が生成しに<<、がっ樹脂との密着強度が高まり、信頼
性の高い樹脂封止形半導体装置が得られる効果がある。As described above, according to the present invention, by providing a mutual diffusion layer of copper and silver on the surface of the lead frame, a copper oxide film is prevented from forming, and the adhesion strength with the resin is increased, resulting in high reliability. This has the effect of providing a resin-sealed semiconductor device.
第1図はこの発明の一実施例による半導体装置用リード
フレームの製造工程を示す概略フロー断面図、第2図は
本発明のリードフレームの酸化皮膜生成の抑制並びに樹
脂との密着強度を示す比較図、第3図は半導体装置用リ
ードフレームの平面図である。
図中、1はリードフレーム素材、2は銅めっき皮膜、3
は銀皮膜、4は銅及び銀の相互拡散層、5はリードフレ
ーム枠、6は半導体素子載置部、7はリード、8は内部
リード、9は外部リード、10はタイバー、11は半導
体封止用樹脂領域を示す。FIG. 1 is a schematic flow sectional view showing the manufacturing process of a lead frame for a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a comparison showing the suppression of oxide film formation and the adhesion strength with resin of the lead frame of the present invention. 3 are plan views of a lead frame for a semiconductor device. In the figure, 1 is the lead frame material, 2 is the copper plating film, and 3 is the lead frame material.
4 is a silver film, 4 is a copper and silver interdiffusion layer, 5 is a lead frame frame, 6 is a semiconductor element mounting part, 7 is a lead, 8 is an internal lead, 9 is an external lead, 10 is a tie bar, 11 is a semiconductor seal The stopper resin area is shown.
Claims (1)
めっき加工が施されたリードフレームであって、少なく
とも半導体素子を搭載する半導体素子載置部と、この半
導体素子載置部の周囲にそれぞれ所定の間隔をもって配
設された複数のリードとをリードフレーム枠に一体に連
結してなる半導体装置用リードフレームにおいて、該リ
ードフレームの表面に薄い銀皮膜を形成した後加熱する
ことにより銅及び銀の相互拡散層を形成したことを特徴
とする半導体装置用リードフレーム。A lead frame made of copper or a copper alloy, or a lead frame whose surface is plated with copper, and includes at least a semiconductor element mounting part on which a semiconductor element is mounted, and a predetermined area around the semiconductor element mounting part. In a lead frame for a semiconductor device in which a plurality of leads disposed at intervals are integrally connected to a lead frame frame, a thin silver film is formed on the surface of the lead frame and then heated to form a bond between copper and silver. A lead frame for a semiconductor device characterized by forming a diffusion layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP571489A JPH02185060A (en) | 1989-01-12 | 1989-01-12 | Lead frame for semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP571489A JPH02185060A (en) | 1989-01-12 | 1989-01-12 | Lead frame for semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02185060A true JPH02185060A (en) | 1990-07-19 |
Family
ID=11618790
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP571489A Pending JPH02185060A (en) | 1989-01-12 | 1989-01-12 | Lead frame for semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02185060A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5561320A (en) * | 1992-06-04 | 1996-10-01 | Texas Instruments Incorporated | Silver spot/palladium plate lead frame finish |
| DE19640256A1 (en) * | 1995-09-29 | 1997-04-03 | Dainippon Printing Co Ltd | Connecting frame for plastics embedded semiconductor component |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63168043A (en) * | 1986-12-27 | 1988-07-12 | Shinko Electric Ind Co Ltd | Lead frame |
-
1989
- 1989-01-12 JP JP571489A patent/JPH02185060A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63168043A (en) * | 1986-12-27 | 1988-07-12 | Shinko Electric Ind Co Ltd | Lead frame |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5561320A (en) * | 1992-06-04 | 1996-10-01 | Texas Instruments Incorporated | Silver spot/palladium plate lead frame finish |
| DE19640256A1 (en) * | 1995-09-29 | 1997-04-03 | Dainippon Printing Co Ltd | Connecting frame for plastics embedded semiconductor component |
| US6034422A (en) * | 1995-09-29 | 2000-03-07 | Dai Nippon Printing Co., Ltd. | Lead frame, method for partial noble plating of said lead frame and semiconductor device having said lead frame |
| DE19640256B4 (en) * | 1995-09-29 | 2004-04-08 | Dai Nippon Printing Co., Ltd. | Lead frame, method for precious metal plating of the lead frame and semiconductor device with lead frame |
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