JPH0221814Y2 - - Google Patents

Description

[Detailed explanation of the idea]

[Industrial application field] This invention is an AC type asynchronous fail-safe type.
It concerns AND circuits. [Prior Art] FIG. 6 is a circuit diagram showing a conventional fail-safe type AND circuit, in which a second D flip-flop
Connect the Q ₂ terminal of F ₂ to the third D flip-flop F ₃ 's R _D3
terminal and said third D flip-flop
Connect the Q ₃ terminal of F ₃ to the fourth D flip-flop F ₄ T ₄
terminal and said third D flip-flop
₃ terminals of F ₃ are connected to the second D flip-flop F ₂
The _T3 terminal of the third D flip-flop _F3 is connected to the R _D4 terminal of the fourth D flip _- flop _F4 .
Connect the D ₂ to _{D 4} terminals of the flip-flops to the power supply P, and connect the second and third D flip-flops to the power supply P.
The T ₂ and T ₃ terminals of F ₂ and F ₃ are used as input terminals, and the fourth
The _Q4 and ₄ terminals of the D flip-flop _F4 are used as output terminals. Terminal to the fail-safe AND circuit of the above configuration.
When two AC inputs P _{1 and} P ₂ are input from O ₁ and O ₂ , this fail-safe AND circuit operates as shown in FIGS. 7 to 10 depending on the phase relationship of the two AC inputs P ₁ and P ₂ . It operates as shown in the time chart. The truth table for AC operation is as shown below.

[Table] Here, the AC excitation state of [H]←→[L] is defined as the DC stable state of [1], [H] or [L].

Define as [0]. Note that the symbols in FIGS. 6 to 10 and the table correspond to each other. [Problems to be solved by the invention] Since the conventional fail-safe type AND circuit is configured as described above, it is clear from the time charts of Figs. 6 to 10 that the AC input
When the phase difference between P ₁ and P ₂ is 0°, the output waveform of Q ₄ is different compared to when there are other phase differences. Therefore, there was a problem in that it interfered with digital calculations using this output. This invention was made to solve the above problems, and the output waveform is the same regardless of the phase difference between the two AC inputs P ₁ and P ₂ from 0° to 360°. The purpose is to obtain an asynchronous fail-safe AND circuit. [Means for solving the problem] Asynchronous fail-safe type according to this invention
The AND circuit is a conventional fail-safe type AND circuit in which a frequency dividing circuit made up of one D flip-flop is added to the input _P2 side of one of the two AC inputs. [Operation] Asynchronous fail-safe type in this invention
The AND circuit connects one of the two AC inputs P ₁ and P ₂ to D
Since the frequency input to the flip-flop is lower than that of the other AC input, the output waveform will be the same even if the phase difference between AC inputs P ₁ and P ₂ is between 0° and 360°. [Example] Hereinafter, an example of this invention will be described with reference to the drawings. As shown in Figure 1, the first
Connect _one terminal of the D flip-flop _F1 to the first D flip-flop F1.
Connect to the _D1 terminal of the flip-flop, and
The _Q1 terminal of the D flip-flop _F1 is connected to the T3 terminal of the third D flip-flop F3 and the R _D4 terminal of the _fourth D flip-flop F4, and the _Q2 terminal of the second D flip-flop F2 is connected to the T3 terminal of the third D flip-flop F3 and the R _D4 terminal of _{the fourth} D flip-flop _F4 . _The Q ₃ terminal of the third D flip-flop _{F 3 is} connected to the T ₄ terminal of the fourth D flip-flop F ₄ . Connect _{the 3 terminals} of the flip-flop F3 to the R _D2 terminal of the second D flip-flop _F2 ,
R _D1 terminal of the first D flip-flop F ₁ and the second to fourth D flip-flops F ₂ to _{F 4}
The D ₂ to _{D 4} terminals of the D flip-flop are connected to the power supply P, the T ₁ and T _{2 terminals of the first and second D flip-flops F 1 and} F ₂ are input terminals, and the Q of the fourth D flip-flop F ₄ is connected to the power supply P. This configuration uses _{the 4} and ₄ terminals as output terminals. The embodiment of this invention has the above configuration, and when two AC inputs P 1 and P ₂ are input from the terminals O ₁ and O ₂ , one of _{the AC inputs P 2 is} connected to the first D
It is frequency-divided by the flip-flop F ₁ to become a lower frequency than the other AC input P ₁ and is supplied to the third and fourth D flip-flops F ₃ and F ₄ . Therefore,
Regardless of whether the phase difference between the two AC inputs P ₁ and P ₂ is between 0° and 360°, the output waveform of Q ₄ will be the same as shown in the time charts of FIGS. 2 to 5. Hereinafter, the specific operation of the embodiment will be explained based on the time chart shown in FIG. First, AC input P ₁
At time A when the input signal is input, the _Q2 terminal of the _second D flip-flop F2 becomes "H", thereby releasing the reset of the third D flip-flop _F3 . Next, at time B when the second AC input _P2 is input after time A, the _Q1 terminal of the first D flip-flop F1 becomes "H", thereby causing the third D flip-flop _F1 to become "H". The _Q3 terminal of flip-flop _F3 becomes "H" and the terminal becomes "L". When the above _Q3 terminal becomes "H", the fourth D flip-flop
_Q4 terminal of _F4 becomes "H", and terminal ₄ becomes "L".
Also, since the above _three terminals become “L”, the second
The D flip-flop _F2 is reset and the _Q2 terminal becomes "L". When this _Q2 terminal becomes "L", the third D flip-flop _F3 is reset, and the _Q3 terminal becomes "L" and _{the Q3} terminal becomes "H". When these _three terminals become "H", the reset of the second D flip-flop _F2 is released. At time C, when AC input P ₁ is input after time B, it is the same as time A. At time D when AC input P ₂ is input after time C above, the first D flip-flop F ₁ is
By the _Q1 terminal becoming “L”, the fourth D
Flip-flop _F4 is reset, and the _Q4 terminal becomes "L" and _{the Q4} terminal becomes "H". At time E, when AC input P ₂ is input after time D, it is the same as time B. Hereinafter, the above operations are sequentially repeated according to the AC inputs P ₁ and P ₂ . Furthermore, due to the phase relationship between the two AC inputs P ₁ and P ₂ , the device operates as shown in the time charts of FIGS. 2, 4, and 5 in accordance with the above. Note that the truth table for AC operation is the same as the previous table. [Effects of the invention] As described above, according to this invention, one of the two AC inputs is input to the D flip-flop and the frequency is divided to a lower frequency than the other AC input, so the phase difference is reduced.
0°~360° different timing (not synchronized)
This has the effect of being able to process two AC inputs input without having to resynchronize.

[Brief explanation of drawings]

Figure 1 is a circuit diagram of an asynchronous fail-safe type AND circuit according to an embodiment of this invention, Figures 2 to 5 are time charts of the circuit, and Figure 6 is a circuit diagram of a conventional fail-safe type AND circuit. , 7th
Figures 1 through 10 are time charts of the circuit. F ₁ to F ₄ are first to fourth D flip-flops;
P is the power supply. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Scope of utility model registration request] Connect _one terminal of the first D flip-flop to the first
The _Q1 terminal of the first D flip-flop is connected to the _D1 terminal of the third D flip-flop.
The _T3 terminal of the flip-flop is connected to the R _D4 terminal of the fourth D flip-flop, the _Q2 terminal of the second D flip-flop is connected to the R D3 terminal of the third D flip-flop, and the Q2 terminal of the second D flip-flop is connected to the R _D3 terminal of the third D flip-flop. The Q ₃ terminal is connected to the T ₄ terminal of the fourth D flip-flop, and _{the 3} terminal of the third D flip-flop is connected to the R _D2 terminal of the second D flip-flop. _{The D1} terminal and the _{D2 to D4} terminals of the second to fourth D flip-flops are connected to a power supply, the _T1 and _T2 terminals of the first and second D flip-flops are used as input terminals, and the fourth An asynchronous fail-safe AND circuit that uses the _Q4 and ₄ terminals of a D flip-flop as output terminals.