JPH0221884A - Japanese pinball game (pachinko) machine - Google Patents

Abstract

PURPOSE:To clearly exhibit occurrence of a specific condition by operating an electrical drive section and a light emitting display section so that movable pieces are opened and closed so as to allow the specific condition to occur while the light emitting display section is lit on or turned on in association with the motion of the movable pieces. CONSTITUTION:Guide blades 1c, 1d as movable pieces which are opened and closed about pivot shafts 1a, 1b in direction in which a pinballs are trapped for a prize wining device 1 are arranged in the center of the prize wining device 1. The guide blades 1c, 1d are connected to rods 2c, 2d constituting parts of solenoids 2a, 2b as electrical drive sections. An 18 cycle-time motion prize wining ball switch 5 giving a specific condition in which the opening and closing of the guide blades 1c, 1d are repeated by 18 times is provided as a successive prize wining detector in successive prize wining port 4. In addition, other two specific prize wining ports are provided on the play game board, being surrounded by guide rails in order to give a specific condition different from that during prize wining operation at the successive prize wining port 4. Light emitting diodes 8a through 8b as parts of a light emitting display section are arranged in front of the prize wining device 1.

Description

Detailed Description of the Invention (Industrial Application Field) The present invention, when a pachinko ball flies into a continuous winning opening, starts to maintain a state that increases the winning probability of a winning device within a predetermined time, and To provide a pachinko machine which starts the winning probability increasing state again from the beginning when a pachinko ball flies into the continuous winning hole again during the winning probability increasing state of the device.

(Prior Art) Conventionally, some pachinko machines change a winning device based on winning balls to generate a specific state in which the probability of winning increases. This type of pachinko machine has a plurality of specific winning holes that generate a specific state on the game board from which pachinko balls are shot, while the winning device has a continuous winning hole that generates a specific state with different conditions from the specific winning holes. It is set up. In addition, specific states with different conditions are set for the plurality of specific winning holes, and the specific state occurs depending on the winning of the specific winning hole. At this time, the pachinko ball becomes easier to enter the winning machine, and if the pachinko ball enters the winning machine and enters the continuous winning slot,
The winning device generates a specific state different from that at the time of winning a specific winning hole.

(Problem to be Solved by the Invention) However, the pachinko machine described above is not specially provided with a means for displaying the occurrence of a specific state, and the specific state is not clearly displayed. If a person misses a prize from a specific winning slot or continuous winning slot,
Although the specific state is perceived by fluctuations in the prize-winning device, there is a loss time until the perception occurs.

In this case, in other words, in a specific situation, it is not possible to effectively utilize the rights advantageous to the player, which increases the probability of winning a prize, so there is a problem that the player's desire to play and the sense of expectation decrease. Furthermore, since the occurrence of a specific state is not clearly displayed, it is not clear to distinguish between the normal game state and the state in which the specific state has occurred, resulting in the problem that the game tends to be monotonous and there is little variation in the game.

Therefore, an object of the present invention is to provide a pachinko machine that is provided with means for clearly displaying the difference between the normal gaming state and the specific state.

(Means for Solving the Problems) Therefore, in order to achieve such an object, the present invention provides a game board from which pachinko balls are shot, which is provided with a specific winning opening and a winning device, and which is connected to the winning device. A movable piece (guide vane) that can be opened and closed with respect to the prize opening and the prize entry device, an electric drive unit (solenoid) that generates a specific state by opening and closing the movable piece, and a lighting display to indicate the specific state of the electric drive unit. an operating circuit (a flip-flop circuit, a reset timing circuit, 8 The configuration is such that it is connected to a binary counter, shift register).

(Function) Since the present invention is configured as described above, the operating circuit operates the electric drive unit and the light emitting display unit based on the winning of the specific winning opening or the continuous winning opening, so that the movable piece opens and closes. While being driven to generate a specific state, the light-emitting display section displays the operation of the movable piece, that is, the occurrence of the specific state, by turning on or off. In addition, the player can touch the light-emitting display section that is displaying a specific state,
It is possible to simultaneously perceive the winning device in which a specific state is occurring.

(Example) An embodiment of the present invention will be described below.

In FIG. 1, l is a winning device according to the present invention, and this winning device Ml is a game board (not shown) on which pachinko balls are launched.
It is located almost in the center of the At the center of this winning device l, guide vanes lc and ld are provided as movable pieces that open in the direction of picking up pachinko balls with respect to the winning device 1, starting from the pivots 1a and lb. That is, the guide vane 1c rotates counterclockwise until it becomes as horizontal as possible, and the guide vane 1d rotates clockwise until it becomes as horizontal as possible. The guide vanes 1c, ld are linked with rods 2c, 2d forming part of solenoids 2a, 2b as electric drive units, as shown in FIG. The guide vanes 1c, ld are opened by driving the solenoids 2a, 2b. As a result, the solenoids 2a and 2b generate a specific state in which the probability of winning a prize increases because the pachinko balls are more likely to flow into the winning device 1. At the bottom of the winning device 1, a partition plate 3.3 is installed upright, and between the partition plates 3 and 3 is a continuous winning opening 4, and this continuous winning opening 4 is equipped with a guide as a continuous winning detector. A 188-turn winning ball switch 5 is provided which generates a specific state in which 188 turns of opening and closing of the blades 1c and ld are performed. In addition to this, in order to generate a specific state different from the continuous winning opening 4 winning, two other specific winning openings (not shown) or provided on the game board surrounded by a guide rail (not shown) are provided. There is.

As shown in Fig. 3, the other specific winning openings marked with - are equipped with a one-time operation winning detector to open and close the guide blades 1c and ld once (specific state). A ball switch 6 is provided.

As shown in Fig. 3, the other two specific winning openings are equipped with two-operation winning detectors for causing guide vanes 1c and ld to open and close twice (specific state). A ball switch 7 is provided. On the front of the winning device l, a light emitting diode 8 is installed as part of a light emitting display section, which will be described later.
8~8g is placed. The game board is provided with a plurality of general winning holes (not shown), and when a pachinko ball wins in one of these, a predetermined number of winnings are paid out for the winning pachinko ball.

FIG. 3 shows the control circuits of the solenoids 2a and 2b, where 9 is a flip-flop circuit, 10 is an 8-bit binary counter circuit, 11 is a Schmitt circuit, 12 is a delay circuit, and 13 is a reset release control box which is a control circuit. Road, 14
15 is a shift register, 15 is a reset timing circuit as an operating circuit, 16 is a clock oscillation circuit, 17 is a light emitting diode blinking circuit as a light emitting display section, and 18 is a sound effect generating circuit as a sound effect generating device. Flip-flop circuit 9.8-bit binary counter circuit 1
0, a Schmitt circuit 11, a delay circuit 12, a shift register 14, a reset timing circuit 15, and a clock oscillation circuit 16 generally constitute an operating circuit.

The configuration and function of the above operating circuit will be explained below.

The flip-flop circuit 9 has a set terminal 5O9S1.
S2. S3, and output terminals QO, Q1. Q2.
Q3, reset terminals RO, R1, R2, R:l,
It has a ground terminal EO, and here, a set terminal S
3. The reset terminal R3 and output terminal Q3 are not used, and the power supply voltage VDD is connected to the set terminal so through the resistor group.
, st, and the Schmitt circuit 11. The power supply voltage VDD is on the high potential side, and each switch 6.7.
5 is in the open state as shown in FIG. 3, the set terminals S O, S 1. S2 has an H input.

The set terminal SO is made to go from H to L when the switch 6 is closed, the set terminal SL is made to go from H to L when the switch 7 is closed, and the set terminal S2 is made to go from H to L when the switch 7 is closed. When the voltage is changed, the voltage changes from H to L. Each output terminal QO~Q2 is each set terminal So~s
2 or H, the output is L, and each set terminal so~s2
When the output voltage is low, the output is high. 19.20 is an OR circuit. The OR circuit 19 outputs an H signal when at least one of the output terminals QO to Q2 of the pre-up flop 9 is H, and the OR circuit 20 outputs an H signal when any one of the output terminals QO, Q2 is H. These OR circuits 19 and 20 have a function of inhibiting the output of each component of the reset timing circuit 15. The Schmitt circuit 11 has an OR gate 21, and the reset release control circuit that controls the operation circuit is composed of a Nant gate.The output of the Schmitt circuit 11 is input to one input terminal of the Nant gate 13, and gate 13
The other input terminal of is connected to the OR circuit 1 via the delay circuit 12.
9 outputs are input. The delay circuit 12 is composed of a group of resistive capacitors, and the function of the delay circuit 12 will be explained together with the configuration of the 8-bit binary counter circuit 10.

The 8-bit binary counter circuit 10 has a reset terminal R.
a, Rb, and output terminals Qoa~Q3a, QOb~Q3b
and input terminals E a and E b. The input terminal Ea is connected to a clock oscillation circuit 16 that generates a lock signal as shown in FIG.
a to Q3a are designed to generate rectangular signals as shown in FIG.

゛The output terminal QOa has a period twice the period of the clock signal and has a function of outputting when the first clock signal is input, and the output terminal Qla has a period four times the period of the clock signal. The output terminal Q2a has a period eight times as long as the period of the clock signal, and has a function of outputting when the second clock signal is input. It has a function to output when input,
The output terminal Q3a has a cycle that is 16 times the cycle of the clock signal, and has a function of outputting when the eighth clock signal is input.

The output of the output terminal Q3a is input to the input terminal Eb, and the output terminal QOb is connected to the output terminal Q as shown in FIG.
It has twice the cycle of the rectangular signal from output terminal Q3a, and has the function of outputting with the first output signal of the rectangular signals from output terminal Q3a, and output terminal Qlb is not used here. , output terminal Q2b has a period eight times as long as the rectangular signal from output terminal Q3a, and
The output terminal Q3b has a function of outputting when the fourth output signal of the rectangular signal from the output terminal Q3b is input.
It has a period 16 times that of the rectangular signal from output terminal Q3a, and has a function of outputting when the eighth rectangular signal from output terminal Q3a is input, and the output from output terminal Q3b is , shift register 14 via inverter element 22
is input to the input terminal CP.

The shift register 14 has the input terminal CP, a reset terminal R1, a power supply potential terminal D, and output terminals QO, Ql, and Q2. The other is connected to the power supply VDD.

As shown in FIG. 5, the output terminal QO of the shift register 14 has a period 32 times that of the rectangular signal from the output terminal Q3a, and the 16th rectangular signal from the output terminal Q3a is input. The output terminal Q1 has a period that is 64 times that of the rectangular signal from the output terminal Q3a, and is not used here.
It has a function of outputting when the 32nd rectangular signal from the output terminal Q3a is input, and the output terminal Q2 is not used here.

Reset terminal Ra of 8-bit binary counter circuit 10
is connected to the delay circuit 12, and the output from the OR circuit 19 is input to the reset terminal Ra with a delay of 0.5 seconds. This reset terminal Ra releases the output from the output terminal QOa when its input is L, and inhibits the output of QOa when its input is H.

The output of the Nandt gate 13 is input to the reset terminal Rh of the 8-bit binary counter circuit 10,
When the input of the reset terminal Rb is H, the output terminal QOb
Output from the output terminal QOb is prohibited, and when the input to the reset terminal Rb is L, the output from the output terminal QOb is released.

The input to the reset terminal Rb is the reset terminal Ra.
When the input becomes H, the signal becomes L at the same time.

The light emitting diode blinking circuit 17 includes two shift registers 23 and 24 as one light emission control device, an OR circuit group 25 as a sequential operation device, a light emitting diode drive circuit 26, and a light emitting diode group 27 as a light emitting section. It is roughly structured.

The shift register 23 has an input terminal CP, a reset terminal R, and output terminals QO to Q3, and the output from the output terminal Q2 of the flip-flop circuit 9 is input to the input terminal CP. The output from the output terminal QOa of the 8-bit binary counter circuit 10 is input.

The outputs from the output terminals QO to Q3 of the shift register 23 are fed back to the input terminals of the shift register 23 via the NOR circuit 28, and the output from the output terminal QO is fed back to the OR circuit 29.
The output from the output terminal Q1 is input to the OR circuit 30 and the OR circuit 34, the output from the output terminal Q2 is input to the OR circuit 31 and the OR circuit 33, and the output from the output terminal Q3 is input to the OR circuit 31 and the OR circuit 35. The output from is input to the OR circuit 32.

The light emitting diode drive circuit 26 has input terminals 10 to I6 and output terminals QO to Q6, the OR circuit 29 controls the output from the output terminal QO, and the OR circuit 30 controls the output from the output terminal Ql. It controls the output of 1
The OR circuit 31 controls the output from the output terminal Q2, the OR circuit 32 controls the output from the output terminal Q3, and the OR circuit 33 controls the output from the output terminal Q4. , the OR circuit 34 is connected to the output terminal Q5
It controls the output from.

The OR circuit 35 controls the output from the output terminal Q6, and the light emitting diodes F8a and 8g are blink-controlled by the output from the output terminal QO of the shift register 23, and the light emitting diodes 8b and 8f are controlled by the output from the output terminal QO of the shift register 23. The light-emitting diodes 8c and 8e are controlled to blink by the output from the output terminal Q2 of the shift register 23, and the light-emitting diode 8d is blinked by the output from the output terminal Q3 of the shift register 23. As shown in FIG. 1, the light emitting diode group 27 is configured so that each diode row blinks from the top to the center toward the center, and the NOR gate 28 realizes a blinking state in which each diode row moves from the top and bottom toward the center. It has a function to repeat this from the beginning once the blinking state is completed.

In addition, when the input of the reset terminal R of the shift register 23 is H, the reset terminal R of the shift register 23 is connected to the output terminals QO to Q of the shift register 23.
The light emitting diode group 27 has a function of inhibiting the output from the output terminal Q2 of the flip-flop circuit 9.
When the output from is H, all lights are turned off.

The shift register 24 has reset terminals Ra, Rb, input terminals Ca, Cb, Db, and output terminals QOa to Q3a.
, Q Ob=Q 2b.

The reset terminals Ra and Rb of the shift register 24 are input with the output of a NOR gate 36, which will be described later.
Two outputs are input. The output of the NOR gate 36 becomes H when the output from this output terminal Q2 is L.
The shift register 24 is to be reset, and when the output from the output terminal Q2 of the flip-flop circuit 9 is H, the output of the NOR gate 36 is L, and the shift register 24 is released from reset. . Therefore, when the shift register 23 is in the reset release state, the shift register 24 is in the reset state,
When the shift register 23 is in the reset state, the shift register 24 is in the reset release state.

The output from the Schmitt circuit 11 is input to input terminals Ca and Cb of the shift register 24 via an inverter element 37. Output terminal Q O of shift register 24
a to Q3a, Q4b"Q6b are connected to OR circuits 29 to 35 in order, respectively, and the output from output terminal Q3a is fed back to input terminal Db, and output terminals Q4b to Q6b are connected to this output terminal. It receives and outputs the output from Q3a, and the output from output terminal Q5b is input to the value input terminal of OR gate 21 forming a part of Schmitt circuit 11.

The OR gate 21 is connected to the output terminal Q6 of the shift register 24.
When there is an output from output terminal Q5b of the shift register 24 and one input terminal of the OR gate 21 is H, the output becomes H. When the terminal is low, it becomes an output signal,
When the output of the output terminal Q6b of the shift register 24 is H, the input to one input terminal of the OR gate 21 is L or H.
The output becomes H regardless of the condition.

When the OR gate 21 opens and closes the 188 rotation winning ball switch 5 once, the output changes from H to L, and the output terminal QOa of the shift register 24 changes from L to H. Along with this, the light emitting diode 8a is also turned on.

When the 188-turn winning ball switch 5 is repeatedly opened and closed eight times, the light emitting diodes 83 to 8g are turned on in this order. When all the light emitting diodes 88 to 8g are lit, the output from the output terminal Q6b of the shift register 24 becomes H, and the input to the value input terminal of the OR gate zt becomes H, so the 188 rotating winning ball switch 5 becomes 8. After opening and closing twice, the output of the OR gate 21 becomes H regardless of whether the 188-turn winning ball switch 5 is opened or closed, and the light emitting diode group 27 is not lit thereafter.

The reset timing circuit 15 includes an ant circuit 38, a NAND circuit 39, a NOR gate 40, and an inverter element 4.
1, a NOAH gate 42, an AND circuit 43, and a NOAH circuit 44, and includes a once-operating winning ball switch 6, a twice-operating winning ball switch 7, or a 188-turn winning ball switch 5 opening/closing (winning ball detection). ), the operation timing of the solenoids 2a and 2b is adjusted accordingly. The outputs of the output terminal Qla and the output terminal Q3a of the 8-bit binary counter circuit 10 are input to the AND circuit 38. The output from the AND circuit 38 and the output from the output terminal QOb of the 8-bit binary counter circuit 10 are input to the NAND circuit 39.

The output from the NAND circuit 39 and the output from the OR circuit 20 are input to the NOR gate 40 .

The output from the output terminal Q2b of the 8-bit binary counter circuit 10 and the output from the output terminal Q2 of the flip-flop circuit 9 are input to the NOR gate 42 via the inverter element 41. The output from the output terminal Q2b of the 8-bit binary counter circuit IO and the output from the output terminal Ql of the shift register 14 are input to the AND circuit 43, and the NOR gate 40, NOR gate 42, and Each output from the circuit 43 and the power supply voltage are input. The output from the NOR circuit 44 is input to each reset terminal RO, R1, R2 of the flip-flop circuit 9, and when the output from the NOR circuit 44 is L,
The output from each output terminal QO to Q2 of the flip-flop circuit 9 is prohibited, and when the output of the NOR circuit 44 is H, the output from each output terminal QO to Q2 of the flip-flop circuit 9 is released. When the NOR gate 40, 42, the AND circuit 43, and the power supply voltage are L, the output of the NOR circuit 44 becomes H, and the flip-flop circuit 9 is released from reset.

The AND circuit 38, the NAND circuit 39, and the NOR gate 40 are used as a reset timing circuit that operates the solenoids 2a and 2b once, and the inverter element 41 and the NOR gate 42 operate the solenoids 2a and 2b once.

The AND circuit 43 operates the solenoids 2a and 2b twice.
It is said to be a reset timing circuit that rotates 88 times.

The NOR gate 40 is connected to the output terminal Q1. of the flip-flop circuit 9. When the output of Q2 is H, its output is always L, and when the output from the output terminal Q2 of the flip-flop circuit 9 is H, its output is L.

Solenoids 2a and 2b are switching circuits 45°4
The switching circuits 45 and 46 are connected to the OR gates 47 and 48 respectively, and the switching circuits 45 and 46 are connected to the OR gates 47 and 48, respectively.
8 is the output terminal QO of the 8-bit binary counter circuit 10
connected to b. The output terminal QOb of the 8-bit binary counter circuit 10 is connected to an AND circuit 49, and the NOR gate 36 and the AND circuit 49 have a function of controlling the sound effect generation circuit 18.
Here, the sound effect is generated when the solenoids 2a and 2b are rotating 188 times, and when the one-time winning ball switch 6 and the two-time winning ball switch 7 are closed. 50 is a display circuit that indicates that the solenoids 2a and 2b are rotating 188 times, and a lamp 52
and an ant circuit 53.

Next, the effect will be explained.

(i) All of the 1-time winning ball switch 6, 2-time winning ball switch 7, and 188 rotating winning ball switches 5 are open, and the set terminals S O, S of the flip-flop circuit 9 are open.
When the input of S2 is low, the input of one input terminal of the OR gate 21 is low, and the input of the other input terminal of H1 is low.

The outputs of the output terminals QO to Q2 of the flip-flop circuit 9 are L, and the output of the OR gate 21 is H, so H is input to one input terminal of the Nant gate 13, and L is input to the other input terminal. The signal is input, and the Nant gate 13 outputs an H level. Therefore, the input to the reset terminal Ra of the 8-bit binary counter circuit 10 is set to L.
Reset terminal Rb of 8-bit binary counter circuit 10
The input of is set to H. Therefore, the reset of the reset terminal Ra of the 8-bit binary counter circuit 10 is released, the output from the output terminal QOa is released, the clock signal from the clock oscillation circuit 16 is output from the output terminal QOa, and the light emitting diode group 27 is the first
As shown in the figure, the blinking state is repeated from the top and bottom of each diode row toward the center. Thereby, the light emitting diode group 27 of the light emitting diode flashing circuit 17 indicates that the pachinko machine is in the normal gaming state, in other words, that the winning device l is not in the specific state. In addition, 1 light emitting diode group 2
7 is provided on the front side of the winning device, so the player can simultaneously perceive the light-emitting display unit displaying the specific state and the opening and closing of the winning device, that is, the guide blades 1c and ld, while the specific state is occurring. Therefore, it is easy to confirm the occurrence of a specific state and the flow path of the pachinko ball.

On the other hand, the reset terminal Rb of the 8-bit binary counter circuit 10 is reset, and the output terminals QOb to Q3b
Output from solenoids 2a and 2b is prohibited.
is in a non-driven state. Therefore, the sound effect generation circuit 18 does not generate sound effects when the pachinko machine is in the normal gaming state.

(ii) When the one-time operation winning ball switch 6 is closed and the input to the value input terminal of the OR gate 21 is L.

When the one-time operation winning ball switch 6 is closed, the set terminal S port of the flip-flop circuit 9 is changed from H to L, and the output from the output terminal QO is changed from L to H. Its output is
8-bit binary counter circuit 1 via delay circuit 12
It is input to the reset terminal Ra of 0 and is also input to the value input terminal of the Nantes gate 13. On the other hand, or gate 21
is outputting H at this time, and its output is input to one input terminal of the Nant gate 13.
3, L is input to the reset terminal Rb of the 8-bit binary counter circuit 10. Note that the input of the reset terminal Rb is set to L when the output of the output terminal QO of the flip-flop circuit 9 changes from L to H. When the output of the output terminal QO of the flip-flop circuit 9 changes from L to H, 8
The reset terminal Ra of the bit binary counter circuit 10 is reset for a time equal to the time constant by the differential circuit of the delay circuit IZ, and output from the output terminals QOa to Q3a is prohibited.

On the other hand, the reset terminal Rb of the 8-bit binary counter circuit 10 is released from reset after the delay time due to the time constant of the integrating circuit of the delay circuit 12 has elapsed, and the reset terminal Rb of the 8-bit binary counter circuit 10 is released from the output terminal QOb-Q3b as shown in FIG. A rectangular signal like this is output. Then, the rectangular signal output from the output terminal QQb is transmitted to the OR gate 47, 48 and the switching circuit 4.
5.46 and is input to the solenoids 2a and 2b, and at the same time, it is input to the NAND circuit 39 and the AND circuit 49.

Therefore, the solenoids 2a and 2b are driven, but one of the AND circuit 38, the NAND circuit 39, and the NOR gate 40 is driven.
With the rotation reset timing circuit, the NAND circuit 39
When the output is low, the NOR circuit 44 outputs low, and the reset terminals RO and R of the flip-flop circuit 9
1 and R2 are reset (see Figure 6).

Therefore, the output terminal QO of the flip-flop circuit 9,
Outputs from Ql and Q2 will be prohibited, solenoids 2a and 2b will be driven for 0.5 seconds as shown in Figure 6, guide vanes 1c and ld will be opened once, and winning device l will be activated. A specific state occurs for only 0.5 seconds. At the same time, the light emitting diode blinking circuit 17 stops the blinking state of the light emitting diode group 27 for 5 seconds to indicate the occurrence of a specific condition, that is, the opening of the guide vanes 1c and ld once.

This allows the player to easily confirm the occurrence of a specific state and the flow path of the pachinko ball.

Further, output from the output terminal Q2 of the flip-flop circuit 9 is prohibited, and the output from the 8-bit binary counter circuit 10 is prohibited.
Since a rectangular signal is output from the output terminal QOb,
The AND circuit 49 inputs this rectangular signal to the sound effect generation circuit 18. Therefore, the sound effect generation circuit 18 determines that the pachinko machine is in a specific state based on the rectangular signal input from the AND circuit 49, that is, the guide blades 1c and 1 of ld.
The opening and closing is indicated by sound effects.

(iii) When the winning ball switch 7 is closed and the input to the value input terminal of the OR gate 21 is L.

When the double-acting π-ball switch 7 is closed, the set terminal S1 of the flip-flop circuit 9 is set to a high level, and the output from the output terminal Q1 is set to a high level. Its output is
Similarly to (ii) above, the signal is inputted to the reset terminal Ra of the 8-bit binary counter circuit 10 via the delay circuit 12, and is also inputted to the other input terminal of the NAND game 13. - On the other hand, the OR gate 21 is outputting H at this time,
The output is input to one input terminal of the Nant gate 13, and from the Nant gate 13, L is input to the reset terminal Rb of the 8-bit binary counter circuit 10. At this time as well, the input to the reset terminal Rb becomes L when the output from the output terminal Q1 of the flip-flop circuit 9 becomes L or H.

When the output of the output terminal Q1 of the flip-flop circuit 9 changes from L to H, the reset terminal Ra of the 8-bit binary counter circuit 10 is reset for a time equal to the time constant by the differential circuit of the delay circuit 12, and the output from the output terminals QOa-Q3a is reset. Output is prohibited.

Further, the reset terminal Rb of the 8-bit binary counter circuit 10 is released from reset, and the output terminals QOb to Q
3b outputs a rectangular signal as shown in FIG.

Therefore, when the solenoids 2a and 2b are driven, or when the NOR gate 42 outputs H due to the two-time reset timing circuit of the inverter element 41 and NOR gate 42, the NOR circuit 44 outputs L, and the flip-flop The reset terminals RO, R1, R2 of the circuit 9 are reset (see FIG. 7).

Therefore, the output terminal QO of the flip-flop circuit 9,
The outputs from Ql and Q2 are prohibited, and the reset terminal Rb of the 8-bit binary counter circuit 10 becomes H, and the solenoids 2a and 2b are reset.
As shown in Figure 7, it is driven only twice for 0.8 seconds each,
The winning device 1 generates a specific state different from that when the one-time winning ball switch 6 described in (ii) is closed. At the same time, the light emitting diode blinking circuit 17 stops the blinking state of the light emitting diode group 27, and indicates the occurrence of a specific state, that is, the opening of the guide vanes 1c and ld twice. Furthermore, similar to (ii), the sound effect generation circuit 18 determines that the pachinko machine is in a specific state based on the rectangular signal input from the AND circuit 49, that is, the guide blade 1c,
The second opening of ld is indicated by sound effects.

(iv) When the 18th operation winning ball switch 5 is closed.

When the 188 rotating winning ball switch 5 is closed, input is only momentary to one input terminal of the OR gate 21, and at this time, input from the output terminal Q6b of the shift register 24 is input to the other input terminal of the OR gate 21. L is input, and L is output from the OR gate 21. The output is input to one input terminal of the Nantes gate 13, and at this time, the guide vane 1
If c and ld are in the middle of the first and second operations, H is input to the other input terminals of the Nantes gate 13, so the Nantes gate 13 momentarily outputs H, and its output is 8. It is input to the reset terminal Rb of the bit binary counter circuit 10. Therefore, the reset terminal Rb is instantaneously reset, and the 8-bit binary counter circuit IO
Output from output terminal QOb is prohibited. Therefore, if the 188-turn winning ball switch 5 is closed during the first and second operations, the first and second operations will immediately end at that point. Further, the output from the OR gate 21 is input to the set terminal S2 of the flip-flop circuit 9, and H is output from the output terminal Q2. The output H is transmitted through the OR circuit 20, the OR circuit 19, and the delay circuit 12 to the (i
As in case i) and (iii), the signal is input to the reset terminal Ra of the 8-bit binary counter circuit 10, and is also input to the other input terminals of the NAND game)-13, and further to the sound effect generation circuit 18. On the other hand, at this time, the 188 rotating winning ball switch 5 is open, H is input to one input terminal of the OR gate 21, H is output from the OR gate 21, and one input terminal of the Nantes gate 13 is H. The L output from the Nant gate 13 is input to the reset terminal Rb of the 8-bit binary counter circuit IO.

In this case, as in (iD(iii)), the input of the reset terminal Rb is the output terminal Q of the flip-flop circuit 9.
When the output of 2 changes from L to H, it is set to L.

Therefore, the reset terminal Ra of the 8-bit binary counter circuit 10 is reset, and output from the output terminals QOa-Q3a is prohibited. Further, the reset terminal Rb of the 8-bit binary counter circuit 10 is released from reset, and a rectangular signal as shown in FIG. 6 is output from the output terminals QOb to Q3b.

Therefore, the solenoids 2a and 2b and the sound effect generation circuit 1
8 is driven, or when the AND circuit 43 outputs H due to the 188 rotation reset timing circuit of the AND circuit 43, the NOR circuit 44 outputs L, and the reset terminal RO of the flip-flop circuit 9 ,R1,R2
is reset (see Figure 8).

Therefore, the output terminal QO of the flip-flop circuit 9,
The outputs from Ql and Q2 are prohibited, and the solenoids 2a and 2b are driven 18 times for 0.8 seconds each as shown in FIG. iii) Displaying a specific state by generating a different sound effect.

In addition, during the 188 rotations of the guide blades 1c and bl, the output of the OR circuit 19 is H, and even if there is a win in the specific winning opening once or twice during the 188 rotations, the OR circuit will not be activated. 19
The output remains H and does not change, so the binary counter circuit 10 is not reset, and the signals caused by the winnings between the 1st and 2nd actions by the 1st action winning ball switch 6 and the 2nd action winning ball switch 7 are ignored. The 188 rotation continues as it is, and the guide vanes 1c and 1d are caused by the light emitting diode blinking circuit 17 and the sound effect generating circuit 18 described above.
There is no indication of the first or second opening.

Since the output from the NOR circuit 44 is input to the reset terminals RO, R1, and R2 of the flip-flop circuit 9, even if there is a win in the 1st and 2nd operation from the specific winning opening during 188 rotations, At the end of 188 rotations, the output terminals QO, Ql, and Q2 of the flip-flop circuit 9 are all reset, so after the completion of 188 rotations, the 1st and 2nd operations due to the winning of the 1st and 2nd operations during the operation will be canceled. Not done.

In addition, when the 188-turn winning ball switch 5 is closed again while the solenoids 2a and 2b are being driven, the input terminal of the OR gate 21 is instantaneously filled with the closing of the 188-turn winning ball switch 5. is input, and L is momentarily output from the OR gate 21 based on it. The output is input to one input terminal of the Nantes gate 13, and at this time, H is input to the other input terminal of the Nantes gate 13, so the Nantes gate 13 momentarily outputs H, and the output is input to the reset terminal Rb of the 8-bit binary counter circuit 10.

Therefore, the reset terminal Rb is momentarily reset,
Output from the output terminal QOb of the 8-bit binary counter circuit 10 is momentarily inhibited (see FIG. 9).

Therefore, the 188-turn rectangular signal from the output terminal QOb of the 8-bit binary counter circuit IO is restarted from the beginning, as shown in FIG.

The H output from the output terminal Q2 of the flip-flop circuit 9 is further input to the reset terminal R of the shift register 23, and is also input to the NOR gate 36 and the sound effect generation circuit 18.
is input. Therefore, output from the set terminals SO to Q3 of the shift register 23 is prohibited, and the light emitting diodes 88 to 8g are all turned off, while L is output from the NOR gate 36, and the output is output from the reset terminal Ra of the shift register 24. Rb and the reset terminal Ra
, Rb are reset.

Further, the sound effect generation circuit 18 displays the specific state by generating sound effects different from (ii) and (iii). At this time,
The output from the OR gate 21 accompanying the closing of the 188 rotary winning ball switch 5 is input to the input terminals Ca and Cb of the shift register 24 via the inverter element 37. H from QOa
is output.

Along with this, the light emitting diode 8a is turned on.

Similarly, during the 18 operations of solenoids 2a and 2b, 1
8 times operation When the winning ball switch 5 is repeatedly opened and closed 8 times,
At No. 11, the light emitting diodes 8b to 8g are lit, and the light emitting diode lighting circuit 17 lights up and displays a specific state different from (ii) and (iii). As a result, (ii) (i
Similar to ii), the player can easily confirm the occurrence of a specific state and the flow path of the pachinko ball while adjusting the ejection means (not shown) for the pachinko ball, making effective use of rights advantageous to the player. can do.

When all the light emitting diodes 88 to 8g are lit, H is output from the output terminal Q6b of the shift register 24,
The inputs of the other input terminals of the OR gate 21 are set to H. Therefore, after the 18@operation winning ball switch 5 opens and closes 8 times, the output of the OR gate 21 is set to H regardless of whether the 18@operation winning ball switch 5 is opened or closed, and the output of the light emitting diode group 2
7 will not be lit thereafter.

In addition, a specific state different from (ii) and (iii), that is, a winning probability increasing state, operates 18 times and when the winning ball switch 5 does not win, the guide blade operates once and 2 times as described above.
Although the game is completed after 18 times, it may be ended when a predetermined number of pachinko balls (for example, 10 balls) win a prize in the winning area of the winning device.

(Effects of the Invention) As is clear from the above description, the present invention provides a normal gaming state and a specific state as a winning probability increased state.
That is, the occurrence of an advantageous right is notified to the player by the light-emitting display section, thereby making it possible to effectively utilize the right. Therefore, the game quality is improved, the game performance is promoted, and the player's desire to play increases.

[Brief explanation of the drawing]

FIG. 1 is a schematic front view showing one embodiment of the present invention, and FIG. 2 is a schematic perspective view showing one embodiment of the present invention. Figure 3 is a control circuit diagram used in the present invention, Figures 4 and 5.
The figures are signal waveform diagrams of clock signals output from each 8-bit binary counter circuit, Figure 6 is a series of signal waveform diagrams when the solenoid is made to open and close once, and Figure 7 is a series of signal waveform diagrams when the solenoid is made to open and close once. Figure 8 is a series of signal waveform diagrams when the solenoid is caused to open and close 18 times. FIG. 9 is a series of signal waveform diagrams when the winning ball switch is closed 18 times while the solenoid is opening and closing 18 times. l...Winning device lc, 1d---Movable piece (guide blade) 2a, 2b-
--Electric drive unit (solenoid) 4... Continuous winning slot 9, 10.11.12.13.14. Is...Operation circuit (flip-flop circuit, 8-bit binary counter circuit, Schmitt circuit, delay circuit, shift register, reset timing circuit, clock oscillation circuit) 17.23.24...Light-emitting display section (light-emitting diode lighting circuit) shift register)

Claims (1)

[Claims] (1) A specific winning hole and a winning device are arranged on the game board from which pachinko balls are shot, and the winning device has a continuous winning hole and a movable piece that can be opened and closed with respect to the winning device, and the movable piece is driven to open and close. an electric drive unit that generates a specific state by doing so, and a light emitting display unit that lights up and displays the specific state of the electric drive unit;
A pachinko machine characterized in that the electric drive unit and the light emitting display unit are connected to an operating circuit that operates according to a winning in the specific winning opening or the continuous winning opening.