JPH0412997B2 - - Google Patents

Description

Detailed Description of the Invention (Industrial Application Field) The present invention, when a pachinko ball flies into a continuous winning opening, starts to maintain a state that increases the winning probability of a winning device within a predetermined time, and To improve a pachinko machine so that when a pachinko ball flies into a continuous winning hole again during the winning probability increasing state of the device, the winning probability increasing state is restarted from the beginning.

(Prior Art) Conventionally, some pachinko machines change a winning device based on winning balls to generate a specific state in which the probability of winning increases. This type of pachinko machine has a plurality of specific winning holes that generate a specific state on the game board from which pachinko balls are shot, while the winning device has a continuous winning hole that generates a specific state with different conditions from the specific winning holes. It is set up. In addition, a specific state with different conditions is set for each of the plurality of specific winning holes, and the specific state occurs depending on the winning of the specific winning hole. At this time, it becomes easier for the pachinko ball to enter the winning machine, and when the pachinko ball enters the winning machine and enters the continuous winning slot, the winning machine generates a specific state that is different from when winning in the specific winning slot. .

(Problem to be Solved by the Invention) However, the pachinko machine described above is not specially provided with means for displaying the occurrence of a specific state, and the specific state is not clearly displayed. Therefore, if the player misses a win in the specific winning hole or the continuous winning hole, he will perceive the specific state through the fluctuation of the winning device, but a loss time will be generated until the player realizes this. In this case, in other words, in a specific situation, it is not possible to effectively utilize the rights advantageous to the player, which increases the winning probability, so there is a problem in that the player's desire to play and the sense of expectation are lowered. In addition, in normal gaming conditions, the player aims the pachinko ball at a specific winning hole or continuous winning hole, while in a specific condition, the player aims the pachinko ball at a place where he can win a large number of winning balls. is aiming for. In this way, the areas to aim for are different in the normal gaming state and the specific state, and it is not easy to predict when the specific state shifts to the normal gaming state. As a result, when transitioning from the specific state to the normal gaming state, it is easy to hit a pachinko ball with inappropriate ball hitting timing and hitting force, and it is easy to generate wasted balls. Furthermore, since the occurrence of a specific state is not clearly displayed, it is not clear to distinguish between the normal gaming state and the specific state occurrence state, resulting in the problem that the game tends to be monotonous and there is little variation in the game.

Therefore, an object of the present invention is to provide a pachinko machine that is provided with means for clearly displaying the difference between the normal gaming state and the specific state.

(Means for Solving the Problems) Therefore, in order to achieve such an object, the present invention provides a winning device into which pachinko balls can fly, and a movable piece (guide blade) that can be opened and closed with respect to the winning device.
, an electric drive unit (solenoid) for driving the movable piece to open and close, a continuation winning slot in which a pachinko ball that has entered the winning machine can win a prize, and the electric drive unit A control circuit (reset release control circuit) for generating a specific state in which the player is driven to open and close a predetermined number of times, and to restart the specific state from the beginning based on a re-winning to the continuous winning opening during the opening and closing operation; The structure includes a light emitting display unit (shift register, reset timing circuit, light emitting diode lighting circuit) for cumulatively lighting up and displaying the progress status of the specific state in accordance with the winning of the continuous winning opening in the specific state. There is.

(Function) Since the present invention is configured as described above, the control circuit operates the electric drive section and the light emitting display section based on the winning of the specific winning hole or the continuous winning hole, so that the movable piece opens and closes. While being driven to generate a specific state, the light-emitting display section displays the operation of the movable piece, that is, the occurrence of the specific state, by turning on or off. In addition, the player can simultaneously perceive the light-emitting display unit that is displaying a specific state and the winning device that is generating a specific state. In addition, the progress status of the specific state is calculated sequentially by the light-emitting display section, and is cumulatively displayed on the light-emitting display section according to the number of times the specific state continues. Status progress can be visually identified.

(Example) An embodiment of the present invention will be described below.

In FIG. 1, reference numeral 1 denotes a winning device according to the present invention, and this winning device 1 is arranged approximately at the center of a game board (not shown) from which pachinko balls are shot. At the center of this winning device 1, there are pivots 1a and 1b.
A guide blade 1 as a movable piece that opens in the direction of picking up pachinko balls with respect to the winning device 1 from the starting point.
c and 1d are provided. That is, the guide vane 1c rotates counterclockwise until it becomes as horizontal as possible, and the guide vane 1d rotates clockwise until it becomes as horizontal as possible. These guide vanes 1c and 1d are
Solenoid 2 as an electric drive as shown in the figure
It is linked with rods 2c and 2d which form part of rods a and 2b. The guide vanes 1c, 1d are opened by driving the solenoids 2a, 2b. This causes solenoid 2
a and 2b generate a specific state in which the probability of winning a prize increases because pachinko balls are more likely to flow into the winning device 1. At the bottom of the winning device 1, partition plates 3, 3 are set up, and between the partition plates 3, 3 is a continuous winning opening 4, and this continuous winning opening 4 is equipped with a guide as a continuous winning detector. Generates a specific state in which blades 1c and 1d open and close 18 times.
There is a winning ball switch 5 that operates 18 times. In addition to this, in order to generate a specific state different from the continuous winning hole 4 winning, other two specific winning holes (not shown)
is provided on the game board surrounded by a guide rail (not shown). As shown in FIG. 3, the other specific winning opening is used as a specific winning detector to open and close the guide blades 1c and 1d once (specific state). A ball switch 6 is provided, and as shown in FIG. 3, a ball switch 6 is provided, and as shown in FIG. A two-time operation winning ball switch 7 is provided to allow the player to win. On the front surface of the winning device 1, light emitting diodes 8a to 8g are arranged as part of a light emitting display section to be described later. The game board is provided with a plurality of general winning holes (not shown), and when a pachinko ball wins in one of these, a predetermined number of winnings are paid out for the winning pachinko ball.

FIG. 3 shows a control circuit for the solenoids 2a and 2b, in which 9 is a flip-flop circuit, 10 is an 8-bit binary counter circuit, 11 is a Schmitt circuit, 12 is a delay circuit, 13 is a reset release control circuit which is a control circuit, 14 is a shift register, 1
5 is a reset timing circuit included in the light emitting display section, 16 is a clock oscillation circuit, 17 is a light emitting diode blinking circuit as the light emitting display section, and 18 is a sound effect generating circuit as a sound effect generating device.

The configuration and function of the above circuit will be explained below.

The flip-flop circuit 9 has set terminals S0,
S1, S2, S3 and output terminals Q0, Q1, Q
2, Q3 and reset terminals R0, R1, R2, R
3 and a ground terminal E0, and here,
Set terminal S3, reset terminal R3, output terminal Q
The power supply voltage VDD, which is not used at 3, is connected to the set terminals S0, S1 and the Schmitt circuit 11 via a group of resistors. The power supply voltage VDD is
The high potential side, and each switch 6, 7, 5 is the third
As shown in the figure, when in the open state, set terminals S0, S1, and S2 are at H level input. The set terminal S0 changes from H to L when the switch 6 is closed, the set terminal S1 changes from H to L when the switch 7 closes, and the set terminal S2 changes from H to L when the switch 5 is closed. When the voltage is changed, the voltage changes from H to L. Each output terminal Q0~Q
2 is set to L output when each set terminal S0 to S2 is H, and when each set terminal S0 to S2 is L,
It is said to be H output. 19 and 20 are OR circuits. The OR circuit 19 outputs an H signal when at least one of the output terminals Q0 to Q2 of the flip-flop 9 is H.
These OR circuits 19 and 20 have the function of inhibiting the output of each component of the reset timing circuit 15. The Schmitt circuit 11 has an OR gate 21, and the reset release control circuit that controls the operation circuit is composed of a NAND gate. The output of the OR circuit 19 is input to the other input terminal via the delay circuit 12. The delay circuit 12 is composed of a group of resistance capacitors,
The function of this delay circuit 12 will be explained together with the configuration of the 8-bit binary counter circuit 10.

The 8-bit binary counter circuit 10 has reset terminals Ra, Rb and output terminals Q0a to Q3a, Q.
0b to Q3b, and input terminals Ea and Eb. The input terminal Ea is connected to a clock oscillation circuit 16 that generates a clock signal as shown in FIG. 4, and each of the output terminals Q0a to Q3a is connected to generate a rectangular signal as shown in FIG. ing.

The output terminal Q0a has a period twice that of the clock signal, has a function of outputting when the first clock signal is input, and has the function of outputting when the first clock signal is input.
has a period four times the period of the clock signal and has a function of outputting when the second clock signal is input, and the output terminal Q2a has a period eight times the period of the clock signal. It has a function of outputting when the fourth clock signal is input, and the output terminal Q3a has a period 16 times the period of the clock signal, and outputs when the eighth clock signal is input. It has the function of outputting to.

The output of the output terminal Q3a is input to the input terminal Eb, and the output terminal Q0b has a period twice that of the rectangular signal from the output terminal Q3a, as shown in FIG. The output terminal Q1b is not used here, and the output terminal Q2b has a period eight times that of the rectangular signal from the output terminal Q3a. It has an output terminal Q3
It has a function of outputting when the fourth output signal of the rectangular signal from a is input, and the output terminal Q3b
has a period 16 times that of the rectangular signal from the output terminal Q3a, has a function of outputting when the eighth output signal of the rectangular signals from the output terminal Q3a is input, and outputs the signal from the output terminal Q3b. The output is input to the input terminal CP of the shift register 14 via the inverter element 22.

The shift register 14 has the input terminal CP reset terminal R, a power supply potential terminal D, and output terminals Q0, Q.
1 and Q2, the output from the NAND gate 13 is input to the reset terminal R, and the power supply potential terminal D is connected to the power supply VDD.

The output terminal Q0 of the shift register 14 receives the rectangular signal from the output terminal Q3a, as shown in FIG.
It has a cycle that is 32 times longer and has a function of outputting when the 16th rectangular signal from output terminal Q3a is input, but it is not used here, and output terminal Q1 is It has a period 64 times that of the rectangular signal from terminal Q3a, and output terminal Q3
It has a function of outputting when the 32nd rectangular signal from a is input, and the output terminal Q2 is not used here.

The reset terminal Ra of the 8-bit binary counter circuit 10 is connected to the delay circuit 12.
The output from the OR circuit 19 is here input to the reset terminal Ra with a delay of 0.5 seconds. This reset terminal Ra releases the output from the output terminal Q0a when its input is L, and inhibits the output of Q0a when its input is H.

The output of the NAND gate 13 is input to the reset terminal Rb of the 8-bit binary counter circuit 10, and when the input to the reset terminal Rb is H, the output from the output terminal Q0b is prohibited, and the input to the reset terminal Rb is disabled. is L, the output terminal Q0
The output from b is what is released. and,
The input to the reset terminal Rb is set to L at the same time as the input to the reset terminal Ra becomes H.

The light emitting diode blinking circuit 17 includes two shift registers 23 and 24 as light emission control devices, an OR circuit group 25 as a sequential operation device, a light emitting diode drive circuit 26, and a light emitting diode group 27 as a light emitting section. It is roughly structured.

The shift register 23 has input terminals D and CP, a reset terminal R, and output terminals Q0 to Q3, and the output from the output terminal Q2 of the flip-flop circuit 9 is input to the input terminal CP.
Output terminal Q0 of bit binary counter circuit 10
The output from a is input.

The outputs from the output terminals Q0 to Q3 of the shift register 23 are fed back to the input terminal D of the shift register 23 via the NOR circuit 28, and the output from the output terminal Q0 is input to the OR circuit 29 and the OR circuit 35. The output from the output terminal Q1 is input to the OR circuit 30 and the OR circuit 34, the output from the output terminal Q2 is input to the OR circuit 31 and the OR circuit 33,
The output from the output terminal Q3 is input to the OR circuit 32.

The light emitting diode drive circuit 26 has an input terminal I0.
~ I6 and output terminals Q0 to Q6, the OR circuit 29 controls the output from the output terminal Q0, the OR circuit 30 controls the output from the output terminal Q1, and the OR circuit 29 controls the output from the output terminal Q1. The circuit 31 controls the output from the output terminal Q2, the OR circuit 32 controls the output from the output terminal Q3, and the OR circuit 33 controls the output from the output terminal Q4. The OR circuit 34 controls the output from the output terminal Q5, the OR circuit 35 controls the output from the output terminal Q6, and the light emitting diodes 8a and 8g control the output from the output terminal Q0 of the shift register 23. The light-emitting diodes 8b and 8f are controlled to blink by the output from the output terminal Q1 of the shift register 23, and the light-emitting diodes 8c and 8e are blinked by the output from the output terminal Q2 of the shift register 23. 8d is controlled to blink by the output from the output terminal Q3 of the shift register 23, and the light emitting diode group 27 is configured so that each diode row is blinked from the top and bottom toward the center as shown in FIG. Noah Gate 28 is
Each diode array has a function of repeating the blinking state from the top to the center from the beginning after the blinking state is completed.

Note that the reset terminal R of the shift register 23 is
When the input is H, the light emitting diode group 27 has a function of inhibiting output from the output terminals Q0 to Q3 of the shift register 23, and when the output from the output terminal Q2 of the flip-flop circuit 9 is H, , all lights are turned off.

The shift register 24 includes reset terminals Ra, Rb and input terminals Ca, Cb, and
Db and output terminals Q0a to Q3a, Q0b to Q2b
It has

The reset terminals Ra and Rb of the shift register 24 are inputted with the output of a NOR gate 36, which will be described later, and the output from the output terminal Q2 of the flip-flop circuit 9 is inputted into the NOR gate 36. When the output from the output terminal Q2 of the NOR gate 36 is L, the output becomes H, and the shift register 24 is reset. When the output from the output terminal Q2 of the flip-flop circuit 9 is H, the output of the NOR gate 36 becomes H. The output becomes L, and the reset of the shift register 24 is released. Therefore, when the shift register 23 is in the reset release state, the shift register 24
is in the reset state, and when the shift register 23 is in the reset state, the shift register 24 is in the reset state.
is set in a reset release state.

The Schmitt circuit 11 is connected to the input terminals Ca and Cb of the shift register 24 via an inverter element 37.
The output from is input. shift register 2
4 output terminals Q0a to Q3a, Q4b to Q6b
are connected to the OR circuits 29 to 35 in order, respectively, and the output from the output terminal Q3a is connected to the input terminal
Db, the output terminals Q4b to Q6b receive and output the output from the output terminal Q3a, and the output from the output terminal Q6b is fed back to the other input terminals of the OR gate 21 forming a part of the Schmitt circuit 11. has been entered.

The OR gate 21 outputs H when the output from the output terminal Q6b of the shift register 24 is L and one input terminal of the OR gate 21 is H.
When the output of the output terminal Q6b of the shift register 24 is L and one input terminal of the OR gate 21 is L, the output becomes L, and when the output of the output terminal Q6b of the shift register 24 is H, the output of the OR gate 21 becomes L. Input to one input terminal is L or H
The output becomes H regardless of the condition.

ORGATE 21 is the 18th operation winning ball switch 5
When is opened and closed once, the output changes from H to L, and the output terminal Q0a of the shift register 24 changes from L to H. Along with this, the light emitting diode 8
A is now lit.

When the 18-time operation winning ball switch 5 is repeatedly opened and closed 8 times, the light emitting diodes 8a to 8g are turned on in this order. When all the light emitting diodes 8a to 8g are turned on, the output from the output terminal Q6b of the shift register 24 becomes H, and the inputs of the other input terminals of the OR gate 21 become H, so that the 18th operation winning ball switch 5 becomes 8. After opening and closing the 18-time winning ball switch 5, the output of the OR gate 21 becomes H, and the light-emitting diode group 27 is no longer lit.

The reset timing circuit 15 is the AND circuit 3
8, a NAND circuit 39, a NOR gate 40, an inverter element 41, a NOR gate 42, an AND circuit 43, and a NOR circuit 44, a one-time winning ball switch 6, a two-time winning ball switch 7, or The operation timing of the solenoids 2a and 2b is determined according to the opening/closing of the 18th operation winning ball switch 5 (winning ball detection). The AND circuit 38 has an output terminal Q1a of the 8-bit binary counter circuit 10.
The outputs of and output terminal Q3a are input. The NAND circuit 39 includes the output from the AND circuit 38 and the output terminal Q of the 8-bit binary counter circuit 10.
The output from 0b is input.

The output from the NAND circuit 39 and the output from the OR circuit 20 are input to the NOR gate 40 . The NOR gate 42 is connected to the output from the output terminal Q2b of the 8-bit binary counter circuit 10 and the flip-flop circuit 9 via the inverter element 41.
The output from the output terminal Q2 is inputted.
The output from the output terminal Q2b of the 8-bit binary counter circuit 10 and the output from the output terminal Q1 of the shift register 14 are input to the AND circuit 43, and the NOR circuit 44 receives the NOR gate 40, the NOR gate 42, Each output of the AND circuit 43 and the power supply voltage are input. The output from the NOR circuit 44 is input to each reset terminal R0, R1, R2 of the flip-flop circuit 9. When the output from the NOR circuit 44 is L, the output from each output terminal Q0 to Q2 of the flip-flop circuit 9 is prohibited,
When the output of the NOR circuit 44 is H, the outputs from the respective output terminals Q0 to Q2 of the flip-flop circuit 9 are released. When the NOR gates 40, 42, AND circuit 43, and the power supply voltage are L, the output of the NOR circuit 44 becomes H, and the flip-flop circuit 9 is released from reset.

The AND circuit 38, the NAND circuit 39, and the NOR gate 40 are used as a reset timing circuit that operates the solenoids 2a and 2b once, and the inverter element 41 and the NOR gate 42 serve as a reset timing circuit that operates the solenoids 2a and 2b twice. The AND circuit 43 is a reset timing circuit that operates the solenoids 2a and 2b 18 times.

The output of the NOR gate 40 is always L when the outputs of the output terminals Q1 and Q2 of the flip-flop circuit 9 are H.
The output is set to L when .

The solenoids 2a and 2b are connected to the switching circuit 4.
5 and 46, respectively, and the switching circuit 4
5 and 46 are connected to OR gates 47 and 48, respectively, and OR gates 47 and 48 are connected to the output terminal Q0b of the 8-bit binary counter circuit 10. The output terminal Q0b of the 8-bit binary counter circuit 10 is connected to an AND circuit 49, and the NOR gate 36 and the AND circuit 49 have a function of controlling the sound effect generation circuit 18. , here solenoids 2a and 2b are
Winning ball switch 6 and 2 during 18th operation and 1st operation
A sound effect is generated when the rotation winning ball switch 7 is closed. 50 is a display circuit that displays that the solenoids 2a and 2b are operating 18 times, and a lamp 52 and an AND circuit 5
It is roughly composed of 3.

Next, the effect will be explained.

(i) The 1-time action winning ball switch 6, the 2-time action winning ball switch 7, and the 18-time action winning ball switch 5 are all open, and the inputs of the set terminals S0, S1, and S2 of the flip-flop circuit 9 are H, When the input to one input terminal of the OR gate 21 is H and the input to the other input terminal is L.

Output terminals Q0 to Q2 of flip-flop circuit 9
The output of is L, and the output of OR gate 21 is H, so H is input to one input terminal of NAND gate 13, L is input to the other input terminal, and H is output from NAND gate 13. be done. Therefore, the input to the reset terminal Ra of the 8-bit binary counter circuit 10 is set to L, and the input to the reset terminal Rb of the 8-bit binary counter circuit 10 is set to L.
The input of is set to H. Therefore, the reset of the reset terminal Ra of the 8-bit binary counter circuit 10 is released, the output from the output terminal Q0a is released, and the clock oscillation circuit 16 is released.
The clock signal is outputted from the output terminal Q0a, and the light emitting diode group 27 repeatedly blinks from the top to the center from the top to the center as shown in FIG. As a result, the light emitting diode group 27 of the light emitting diode flashing circuit 17 indicates that the pachinko machine is in the normal gaming state, in other words, that the winning device 1 is not in the specific state. Also,
Since the light emitting diode group 27 is provided on the front side of the winning device, the player simultaneously perceives the light emitting display unit displaying a specific state and the opening and closing of the winning device, that is, the guide wings 1c and 1d, while the specific state is occurring. Therefore, it is easy to confirm the occurrence of a specific state and to confirm the flow path of the pachinko ball.

On the other hand, the reset terminal Rb of the 8-bit binary counter circuit 10 is reset, output from the output terminals Q0b to Q3b is prohibited, and the solenoids 2a and 2b are not driven.
Therefore, the sound effect generation circuit 18 does not generate sound effects when the pachinko machine is in the normal gaming state.

(ii) When the one-time operation winning ball switch 6 is closed and the input to the other input terminal of the OR gate 21 is L.

When the one-time winning ball switch 6 is closed, the set terminal S0 of the flip-flop circuit 9 is changed from H to L, and the output from the output terminal Q0 is changed from L to H. The output is sent to the reset terminal of the 8-bit binary counter circuit 10 via the delay circuit 12.
The signal is input to Ra and is also input to other input terminals of the NAND gate 13. On the other hand, ORGATE 21 is
At this time, H is output, and its output is input to one input terminal of the NAND gate 13, and from the NAND gate 13, L is input to the reset terminal Rb of the 8-bit binary counter circuit 10. still,
The input to the reset terminal Rb is set to L when the output of the output terminal Q0 of the flip-flop circuit 9 changes from L to H. When the output of the output terminal Q0 of the flip-flop circuit 9 changes from L to H, the reset terminal Ra of the 8-bit binary counter circuit 10 becomes
The time constant is reset by the differentiating circuit of the delay circuit 12, and output from the output terminals Q0a to Q3a is prohibited.

On the other hand, the reset terminal Rb of the 8-bit binary counter circuit 10 is released from reset after the delay time due to the time constant of the integrating circuit of the delay circuit 12 has elapsed, and the fifth
A rectangular signal as shown in the figure is output. and,
The rectangular signal output from the output terminal Q0b is sent to OR gates 47, 48 and switching circuits 45, 4.
6 to the solenoids 2a and 2b, and simultaneously to the NAND circuit 39 and the AND circuit 49.

Therefore, the solenoids 2a and 2b are driven, but due to the one-time operation reset timing circuit of the AND circuit 38, NAND circuit 39, and NOR gate 40, when L is output from the NAND circuit 39, L is output from the NOR circuit 44. The reset terminals R0, R1, and R2 of the flip-flop circuit 9 are reset (see FIG. 6).

Therefore, the output from the output terminals Q0, Q1, and Q2 of the flip-flop circuit 9 is prohibited, and the solenoids 2a and 2b are driven for only 0.5 seconds as shown in FIG. 6, and the guide vanes 1c and 1d are driven.
is opened once, and a specific state occurs in the winning device 1 for only 0.5 seconds. At the same time, the light emitting diode blinking circuit 17 stops the blinking state of the light emitting diode group 27 for 0.5 seconds to indicate the occurrence of a specific state, that is, one opening of the guide vanes 1c and 1d. This allows the player to easily confirm the occurrence of a specific state and the flow path of the pachinko ball.

Furthermore, the output terminal Q of the flip-flop circuit 9
Since the output from the 8-bit binary counter circuit 10 is prohibited and a rectangular signal is output from the output terminal Q0b of the 8-bit binary counter circuit 10, the AND circuit 49 inputs this rectangular signal to the sound effect generating circuit 18. Therefore, the sound effect generating circuit 18 determines that the pachinko machine is in a specific state based on the rectangular signal input from the AND circuit 49, that is, the guide blades 1c and 1d are
The opening is indicated by the generation of a sound effect.

(iii) When the two-time operation winning ball switch 7 is closed and the input to the other input terminal of the OR gate 21 is L.

When the double-operation winning ball switch 7 is closed, the set terminal S1 of the flip-flop circuit 9 changes from H to L, and the output from the output terminal Q1 changes from L to H. The output is sent to the delay circuit 1 as in (ii) above.
2 to the reset terminal Ra of the 8-bit binary counter circuit 10, and also to other input terminals of the NAND gate 13. On the other hand, the OR gate 21 is outputting H at this time, and its output is input to one input terminal of the NAND gate 13, and from the NAND gate 13, L is input to the reset terminal Rb of the 8-bit binary counter circuit 10. . Also at this time, the input to the reset terminal Rb is set to L when the output from the output terminal Q1 of the flip-flop circuit 9 changes from L to H.

When the output of the output terminal Q1 of the flip-flop circuit 9 changes from L to H, the reset terminal Ra of the 8-bit binary counter circuit 10 is reset for a time equal to the time constant by the differential circuit of the delay circuit 12, and the outputs from the output terminals Q0a to Q3a are reset. is prohibited. Further, the reset terminal Rb of the 8-bit binary counter circuit 10 is released from reset, and rectangular signals as shown in FIG. 5 are output from the output terminals Q0b to Q3b.

Therefore, the solenoids 2a and 2b are driven, but due to the two-time reset timing circuit of the inverter element 41 and the NOR gate 42, when the NOR gate 42 outputs an H level, the NOR circuit 44 outputs an L level, and the flip-flop circuit The reset terminals R0, R1, and R2 of 9 are reset (see FIG. 7).

Therefore, the output from the output terminals Q0, Q1, and Q2 of the flip-flop circuit 9 is prohibited, and the reset terminal Rb of the 8-bit binary counter circuit 10 becomes H, and the solenoids 2a and 2b are reset. As shown in Figure 7
It is driven only twice for 0.8 seconds each, and the winning device 1 is
A specific state different from that when the one-time action winning ball switch 6 is closed as described in (ii) is generated. At the same time, the light emitting diode blinking circuit 17 stops the blinking state of the light emitting diode group 27, and indicates the occurrence of a specific state, that is, the opening of the guide vanes 1c and 1d twice. Furthermore, similar to (ii), the sound effect generation circuit 18 generates a sound effect to indicate that the pachinko machine is in a specific state, that is, the guide blades 1c and 1d are opened twice, based on the rectangular signal input from the AND circuit 49. Displayed by occurrence.

(iv) When the 18th operation winning ball switch 5 is closed.

When the 18th operation winning ball switch 5 is closed, L is momentarily input to one input terminal of the OR gate 21, and at this time, L is input from the output terminal Q6b of the shift register 24 to the other input terminal of the OR gate 21. is input, and L is output from the OR gate 21. The output is input to one input terminal of the NAND gate 13, and at this time, if the guide vanes 1c and 1d are in the middle of the first and second operations, the NAND gate 1
Since H is input to the other input terminal of 3, the NAND gate 13 momentarily outputs H, and the output is sent to the 8-bit binary counter circuit 1.
0 reset terminal Rb. Therefore, the reset terminal Rb is instantaneously reset, and the output from the output terminal Q0b of the 8-bit binary counter circuit 10 is prohibited. Therefore, once and twice
If the 18th round winning ball switch 5 is closed during the rounding motion, the 1st and 2nd round motions will immediately end at that point. Also, the output from the OR gate 21 is
The signal is input to the set terminal S2 of the flip-flop circuit 9, and H is output from the output terminal Q2. The output H is sent to the reset terminal Ra of the 8-bit binary counter circuit 10 via the OR circuit 20, the OR circuit 19, and the delay circuit 12, as in the cases (ii) and (iii) above.
The signal is input to the NAND gate 13, other input terminals, and further to the sound effect generation circuit 18.
On the other hand, at this time, the winning ball switch 5 operates 18 times.
is open, H is input to one input terminal of the OR gate 21, H is output from the OR gate 21, one input terminal of the NAND gate 13 is set to H, and an L output is output from the NAND gate 13. 8
Reset terminal of bit binary counter circuit 10
Input to Rb.

In this case, as in (ii) and (iii) above, the reset terminal
The input of Rb is set to L when the output of the output terminal Q2 of the flip-flop circuit 9 changes from L to H.

Therefore, the 8-bit binary counter circuit 10
The reset terminal Ra of is reset, and the output terminal Q
Outputs from 0a to Q3a are prohibited. Also, 8
Reset terminal of bit binary counter circuit 10
Rb is reset and output terminal Q0b~
A rectangular signal as shown in FIG. 5 is output from Q3b.

Therefore, the solenoids 2a and 2b and the sound effect generating circuit 18 are driven, but the 18 of the AND circuit 43 is driven.
When the AND circuit 43 outputs H, the NOR circuit 44 is activated by the rotation reset timing circuit.
L is output from the flip-flop circuit 9, and reset terminals R0, R1, and R2 of the flip-flop circuit 9 are reset (see FIG. 8).

Therefore, output from the output terminals Q0, Q1, and Q2 of the flip-flop circuit 9 is prohibited, and the solenoids 2a and 2b are driven only 18 times for 0.8 seconds each as shown in FIG. At the same time as the game state is shifted to the specific state, the specific state is displayed by generating sound effects different from (ii) and (iii) by the sound effect generating circuit 18.

In addition, during the 18th operation of the guide blades 1c and 1d, the output of the OR circuit 19 is H, and even if there is a win in the 1st or 2nd operation to the specific winning opening during the 18th operation, the OR circuit will not be activated. The output of 19 remains at H and does not change, so the binary counter circuit 10 is not reset, and the winnings between the 1st and 2nd actions by the 1st action winning ball switch 6 and the 2nd action winning ball switch 7 are not reset. The signal is ignored and the 18th operation continues as it is, and there is no indication that the guide vanes 1c and 1d are opened once or twice by the light emitting diode blinking circuit 17 and the sound effect generating circuit 18 described above.

Since the output from the NOR circuit 44 is input to the reset terminals R0, R1, and R2 of the flip-flop circuit 9, the output from the specific winning opening is 18 times during the 18th operation.
Even if there is a winning prize for the 18th and 2nd operation, the output terminal Q of the flip-flop circuit 9 will be
Since 0, Q1, and Q2 are all reset, after the 18th operation is completed, the 1st and 2nd operations will not be performed due to the winning of the 1st and 2nd operations during the relevant operation.

In addition, when the 18th operation winning ball switch 5 is closed again while the solenoids 2a and 2b are being driven,
L is momentarily input to the input terminal of the OR gate 21 by closing the 18-time winning ball switch 5, and L is momentarily output from the OR gate 21 based on this. The output is input to one input terminal of the NAND gate 13, and at this time, H is input to the other input terminal of the NAND gate 13, so the NAND gate 13 momentarily outputs H, and the output is 8 It is input to the reset terminal Rb of the bit binary counter circuit 10. Therefore,
The reset terminal Rb is momentarily reset, and the output terminal Q0b of the 8-bit binary counter circuit 10 is reset.
output is momentarily inhibited (see Figure 9).

Therefore, 8-bit binary counter circuit 1
The 18-time operation rectangular signal from output terminal Q0b of
As shown in FIG. 9, the process starts again from the beginning.

The H output from the output terminal Q2 of the flip-flop circuit 9 is further input to the reset terminal R of the shift register 23, as well as to the NOR gate 36 and the sound effect generating circuit 18. Therefore,
Output from the set terminals S0 to Q3 of the shift register 23 is prohibited, and the light emitting diodes 8a to 8g are all turned off, while L is output from the NOR gate 36, and the output is sent to the reset terminals Ra and Rb of the shift register 24. input, the reset terminal
The reset of Ra and Rb is canceled.

Further, the sound effect generating circuit 18 displays the specific state by generating different sound effects as in (ii) and (iii). At this time, input terminals Ca and Cb of the shift register 24 have
The output from the OR gate 21 accompanying the closing of the 18-time winning ball switch 5 is inputted via the inverter element 37, and H is output from the output terminal Q0a of the shift register 24. Along with this, the light emitting diode 8a is connected to the shift register 24.
The reset timing circuit 15 cumulatively lights up and displays the number of wins in the continuous winning hole 4 in the specific state that has been calculated, that is, the progress status of the specific state. This allows the player to visually identify the progress of the specific state according to the changes in the lighting display of the light emitting diode blinking circuit.

Similarly, when the 18th operation winning ball switch 5 is repeatedly opened and closed 8 times during the 18th operation of the solenoids 2a and 2b, the light emitting diodes 8b to 8g are lit in this order, and the light emitting diode lighting circuit 17 is activated as shown in (ii). ,(iii)
Lights up to indicate a specific state that is different from the actual state. This results in
Similar to (ii) and (iii), the player can easily confirm the occurrence of a specific state and the flow path of the pachinko ball while adjusting the ejection means (not shown) for the pachinko ball, which is advantageous for the player. Rights can be used effectively.

When all the light emitting diodes 8a to 8g are turned on, H is output from the output terminal Q6b of the shift register 24, and the inputs of the other input terminals of the OR gate 21 are set to H. Therefore, after the 18-time winning ball switch 5 opens and closes 8 times, the output of the OR gate 21 becomes H regardless of whether the 18-time winning ball switch 5 is opened or closed, and the light emitting diode group 27 does not light up after that. do not have.

In addition, the specific state different from (ii) and (iii), that is, the winning probability increasing state, operates 18 times.If the winning ball switch 5 does not win, the guide blade operates once and twice as described above, and further 18 times. Although the game ends with the turning operation, it may also end when a predetermined number of pachinko balls (for example, 10 balls) win a prize in the winning area of the winning device.

(Effects of the Invention) As is clear from the above description, the present invention enables the normal gaming state and the specific state as the winning probability increased state, that is, the generation of advantageous rights, to
A light emitting display section informs the player,
It is possible to make effective use of such rights. Therefore, the game quality is enhanced, the game performance is promoted, and the player's desire to play increases. Further, since the player can visually clearly identify the progress of the specific state according to the change in the lighting display of the light emitting display section, the player can easily adjust the batting force and timing according to the progress of the specific state. From this, advantageous rights that arise in a particular state can be effectively exercised. Furthermore, since the light-emitting display section gradually changes as the number of continuations of the specific state increases, visual changes in the game increase.

[Brief explanation of drawings]

FIG. 1 is a schematic front view showing one embodiment of the present invention, FIG. 2 is a schematic perspective view showing one embodiment of the present invention, FIG. 3 is a control circuit diagram used in the present invention, and FIG. 5 is a signal waveform diagram of the clock signal output from the 8-bit binary counter circuit, FIG. 6 is a series of signal waveform diagrams when the solenoid is made to open and close once, and FIG. , a series of signal waveform diagrams when the solenoid is made to open and close twice, Figure 8 is a series of signal waveform diagrams when the solenoid is made to open and close 18 times, and Figure 9 is a series of signal waveform diagrams when the solenoid opens and closes 18 times. It is a series of signal waveform diagrams when the 18-time operation winning ball switch is closed during operation. 1... Prize winning device, 1c, 1d... Movable piece (guide vane), 2a, 2b... Electric drive unit (solenoid), 4
…Continuous prize opening, 9, 10, 11, 12, 13, 1
4, 16...Operation circuit (flip-flop circuit, 8
Bit binary counter circuit, Schmitt circuit,
delay circuit, shift register, reset timing circuit, clock oscillation circuit), 17, 23, 24...
Light emitting display section (light emitting diode lighting circuit shift register).

Claims (1)

[Claims] 1. A winning device into which a pachinko ball can enter, a movable piece that can be opened and closed with respect to the winning device, an electric drive unit for driving the movable piece to open and close, and a pachinko ball that has entered the winning device. Possible continuous winning openings and
Generating a specific state in which the electric drive unit is driven to open and close a predetermined number of times based on a winning in the continuous winning opening, and also restarting the specific state from the beginning based on a re-winning in the continuous winning opening during the opening/closing operation. A pachinko machine characterized by having a control circuit for starting the game, and a light-emitting display section for cumulatively lighting up and displaying the progress status of the specific state in accordance with winnings in the continuous winning opening in the specific state. .