JPH0367714B2 - - Google Patents

Description

Detailed Description of the Invention (Industrial Application Field) The present invention, when a pachinko ball flies into a continuous winning opening, starts to maintain a state that increases the winning probability of a winning device within a predetermined time, and To provide a pachinko machine which starts the winning probability increasing state again from the beginning when a pachinko ball flies into the continuous winning hole again during the winning probability increasing state of the device.

(Prior Art) Conventionally, some pachinko machines increase the winning probability of a winning device using winning balls. This type of pachinko machine has a specific winning hole and a winning device arranged on the game board from which pachinko balls are shot, and this winning device has a continuous winning hole and a movable piece that can be opened and closed with respect to the winning device.
An electric drive unit that drives the movable piece to open and close, and a drive circuit that generates a drive signal for the electric drive unit are provided. The specific winning hole and the continuous winning hole are for increasing the winning probability, and when a pachinko ball enters the specific winning hole, the drive circuit generates a drive signal. Then, based on the generation of this drive signal, the electric drive section opens and closes the movable piece once or twice, making it easier for the pachinko ball to enter the winning device.
The probability of winning increases.

When the winning probability increases, when the pachinko ball enters the winning device and further enters the continuous winning slot, the drive circuit generates a drive signal different from that when winning a specific winning slot, and generates this drive signal. Based on this, the electric drive opens and closes the movable piece 18 times. For this reason, the winning device continuously increases the winning probability of pachinko balls, and rights advantageous to the technician are continuously generated. In addition, if a prize is entered into the continuous winning slot again while the movable piece has been opened and closed 18 times, the right will be renewed and the 18th opening and closing of the movable piece will start from the beginning, and this renewal will be repeated 8 times. will continue until

When playing a pachinko game using such a pachinko machine, the player increases the possibility that the movable piece will open and close once or twice by aiming at a specific winning opening during a normal game. As a result, the player can increase the probability that more pachinko balls will enter the winning device and also enter the continuous winning slot, so that rights advantageous to the player will continue to occur. In addition, if the player wins a prize in the winning device while the movable piece is opening and closing once or twice, and then wins in the continuous winning slot, in order to effectively utilize the rights advantageous to the player, the player The movable piece is aimed so that the ball is most likely to enter a winning device. As a result, a large number of prize balls can be expected to be paid out compared to the normal game.

In addition, the time required for opening and closing the movable piece based on a winning of the specific winning opening is set to about 0.5 seconds in the case of 1 time, and 0.8 seconds per time in the case of 2 times and 18 times. In addition, the winning probability in such a pachinko machine has been increased by causing the drive circuit to generate a drive signal immediately after a winning in a specific winning hole or continuous winning hole.

(Problem to be Solved by the Invention) However, during normal gaming, the player is aiming at a specific winning opening, so the winning state of the specific winning opening is visually observed, and the winning device is not visible from the player's field of view. It's off. In addition, the opening/closing of the movable piece based on a winning of a specific winning opening is about 0.5 seconds or 0.8 seconds, so if you are aiming at a specific winning opening, the opening/closing of the movable piece based on a winning of a specific winning opening is about 0.5 seconds or 0.8 seconds. You may miss it. In this case, the player cannot visually see whether or not the pachinko ball will win in the winning device, and furthermore, if the pachinko ball enters the winning device, whether or not it will enter the continuous winning hole. In other words, since it is not possible to visually check whether or not rights advantageous to the player will continue to occur, there is a problem in that expectations and changes in the game are reduced.

Therefore, an object of the present invention is to provide a pachinko machine in which opening/closing and updating of a movable piece based on a winning of a specific winning opening can be perceived.

(Means for Solving the Problems) Therefore, in order to solve such problems, the present invention provides drive circuit control that generates a drive signal when a preset wait time has elapsed from the time of winning a prize in a specific winning opening. The configuration includes an operating circuit for

(Function) Since the present invention is configured as described above, the drive circuit causes the operation circuit to generate a drive signal after the wait time has elapsed since the pachinko ball entered the specific winning hole. Thereby, if a pachinko ball enters a specific winning hole and the player visually observes the movable piece before the wait time elapses, he or she can perceive whether the movable piece is opened or closed.

(Example) An embodiment of the present invention will be described below.

In FIG. 1, 1 is a winning device according to the present invention, and in the center of this winning device 1 are pivots 1a, 1b.
Guide vanes 1c and 1d are provided as movable pieces that open in the direction of picking up pachinko balls from the starting point. That is, the guide vane 1c rotates counterclockwise until it becomes as horizontal as possible, and the guide vane 1d rotates clockwise until it becomes as horizontal as possible. The guide vanes 1c, 1b are linked with rods 2c, 2d forming part of solenoids 2a, 2b as electric drive units, as shown in FIG. The guide vanes 1c, 1d are opened by driving the solenoids 2a, 2b.
At the bottom of the winning device 1, partition plates 3, 3 are set up, and between the partition plates 3, 3 is a continuous winning opening 4, and this continuous winning opening 4 is equipped with a continuous winning detector 18. An 18-time operation winning ball switch 5 is provided for causing the rotation operation. In addition to this,
Two other specific winning holes (not shown) are provided, and as shown in FIG. A two-time action winning ball switch 6 is provided, and a two-time action winning ball switch 7 is provided in the other two specific winning holes, as shown in FIG. It is provided. On the front surface of the winning device 1, light emitting diodes 8a to 8g are arranged as part of the notification means.

FIG. 3 shows a drive circuit for the solenoids 2a and 2b, which includes a flip-flop circuit 9, an 8-bit binary counter circuit 10, a Schmitt circuit 11, a delay circuit 12, a reset release drive circuit 13, and a shift circuit as an operating circuit. register 14
The main components are a reset timing circuit 15 and a reset timing circuit 15. Further, 16 is a clock oscillation circuit, 17 is a light emitting diode blinking circuit as a notification means, and 18 is a sound effect generation circuit as a notification means.

The configuration and function of each of these circuits will be explained below.

The flip-flop circuit 9 has set terminals S0,
S1, S2, S3 and output terminals Q0, Q1, Q
2, Q3 and reset terminals R0, R1, R2, R
3 and a ground terminal E0, and here,
Set terminal S3, reset terminal R3, output terminal Q
3 is not used. The power supply voltage VDD is continued to the set terminals S0, S1 and the Schmitt circuit 11 via a group of resistors. The power supply voltage VDD is
The high potential side, and each switch 6, 7, 5 is the third
As shown in the figure, when in the open state, set terminals S0, S1, and S2 are at H level input. The set terminal S0 changes from H to L when the switch 6 is closed, the set terminal S1 changes from H to L when the switch 7 closes, and the set terminal S2 changes from H to L when the switch 5 is closed. When the voltage is changed, the voltage changes from H to L. Each output terminal Q0~Q
2 is set to L output when each set terminal S0 to S2 is H, and when each set terminal S0 to S2 is L,
It is said to be H output. 19 and 20 are OR circuits. The OR circuit 19 outputs an H signal when at least one of the output terminals Q0 to Q2 of the flip-flop 9 is H.
These OR circuits 19 and 20 have a function of inhibiting the output of each component of the reset timing circuit 15. Schmitt circuit 11
has an OR gate 21, and the reset release control circuit 13 that controls the 8-bit binary counter circuit 10 is composed of a NAND gate.
1 is input, and an OR circuit 19 is input to the other input terminal of the NAND gate 13 via the delay circuit 12.
The output of is input. The delay circuit 12 is composed of a group of resistor capacitors, and the function of this delay circuit 12 is that of the 8-bit binary counter circuit 1.
This will be explained together with the configuration of 0.

The 8-bit binary counter circuit 10 has reset terminals Ra, Rb and output terminals Q0a to Q3a, Q.
0b to Q3b, and input terminals Ea and Eb. The input terminal Ea is connected to a clock oscillation circuit 16 that generates a clock signal as shown in FIG. 4, and each of the output terminals Q0a to Q3a generates a rectangular signal as shown in FIG. There is.

The output terminal Q0a has a period twice that of the clock signal, has a function of outputting when the first clock signal is input, and has the function of outputting when the first clock signal is input.
has a period four times the period of the clock signal and has a function of outputting when the second clock signal is input, and the output terminal Q2a has a period eight times the period of the clock signal. It has a function of outputting when the fourth clock signal is input, and the output terminal Q3a has a period 16 times the period of the clock signal, and outputs when the eighth clock signal is input. It has the function of outputting to.

The output of the output terminal Q3a is input to the input terminal Eb, and the output terminal Q0b has a period twice that of the rectangular signal from the output terminal Q3a, as shown in FIG. It has a function of causing the output H to rise when the first output signal of the rectangular signal, that is, the eighth clock signal, is input and falls (see FIG. 6). Also,
Output terminal Q1b is not used here,
The output terminal Q2b has a period eight times that of the rectangular signal from the output terminal Q3a, and has a function of outputting when the fourth output signal of the rectangular signals from the output terminal Q3a is input. The output terminal Q3b is
The period is 16 times that of the rectangular signal from output terminal Q3a, and the 8th period of the rectangular signal from output terminal Q3a is
The output of the output terminal Q3b is transmitted to the input terminal of the shift register 14 via the inverter element 22.
It is entered in CP.

The shift register 14 has the input terminal CP, the reset terminal R, the power supply potential terminal D, the output terminal Q0,
Q1 and Q2, and the reset terminal R has
The output from the NAND gate 13 is input, and the power supply potential terminal D is connected to the power supply VDD.

The output terminal Q0 of the shift register 14 receives the rectangular signal from the output terminal Q3a, as shown in FIG.
It has a cycle that is 32 times longer and has the function of outputting when the 16th rectangular signal is input from output terminal Q3a, but it is not used here, and output terminal Q1 is It has a period 64 times that of the rectangular signal from terminal Q3a, and output terminal Q3
It has a function of outputting when the 32nd rectangular signal from a is input, and the output terminal Q2 is not used here.

The reset terminal Ra of the 8-bit binary counter circuit 10 is connected to the delay circuit 12, and the output from the OR circuit 19 is input to the reset terminal Ra after a delay of 0.5 seconds. This reset terminal Ra releases the output from the output terminal Q0a when its input is L, and inhibits the output of Q0a when its input is H.

The output of the NAND gate 13 is input to the reset terminal Rb of the 8-bit binary counter circuit 10, and when the input to the reset terminal Rb is H, the output from the output terminal Q0b is prohibited, and the input to the reset terminal Rb is disabled. is L, the output terminal Q0
The output from b is what is released. and,
The input to the reset terminal Rb is set to L at the same time as the input to the reset terminal Ra becomes H.

The light emitting diode blinking circuit 17 includes two shift registers 23 and 24, an OR circuit group 25, a light emitting diode drive circuit 26, and a light emitting diode group 27.
It is roughly composed of.

The shift register 23 has input terminals D and CP, a reset terminal R, and output terminals Q0 to Q3, and the output from the output terminal Q2 of the flip-flop circuit 9 is input to the input terminal CP.
Output terminal Q0 of bit binary counter circuit 10
The output from a is input.

The outputs from the output terminals Q0 to Q3 of the shift register 23 are fed back to the input terminal D of the shift register 23 via the NOR circuit 28, and the output from the output terminal Q0 is input to the OR circuit 29 and the OR circuit 35. The output from the output terminal Q1 is input to the OR circuit 30 and the OR circuit 34, the output from the output terminal Q2 is input to the OR circuit 31 and the OR circuit 33,
The output from the output terminal Q3 is input to the OR circuit 32.

The light emitting diode drive circuit 26 has an input terminal I0.
~ I6 and output terminals Q0 to Q6, the OR circuit 29 controls the output from the output terminal Q0, the OR circuit 30 controls the output from the output terminal Q1, and the OR circuit 29 controls the output from the output terminal Q1. The circuit 31 controls the output from the output terminal Q2, the OR circuit 32 controls the output from the output terminal Q3, and the OR circuit 33 controls the output from the output terminal Q4. The OR circuit 34 controls the output from the output terminal Q5, the OR circuit 35 controls the output from the output terminal Q6, and the light emitting diodes 8a and 8g control the output from the output terminal Q0 of the shift register 23. The light-emitting diodes 8b and 8f are controlled to blink by the output from the output terminal Q1 of the shift register 23, and the light-emitting diodes 8c and 8e are blinked by the output from the output terminal Q2 of the shift register 23. 8d is controlled to blink by the output from the output terminal Q3 of the shift register 23, and the light emitting diode group 27 is configured to achieve a blinking state in which each diode row moves from the top to the center toward the center, as shown in FIG. The NOR gate 28 has a function of repeating the blinking state once again from the beginning after each diode array completes the blinking state from the top and bottom toward the center.

Note that the reset terminal R of the shift register 23 is
When the input is H, the light emitting diode group 27 has a function of inhibiting output from the output terminals Q0 to Q3 of the shift register 23, and when the output from the output terminal Q2 of the flip-flop circuit 9 is H, , all lights are turned off.

The shift register 24 has reset terminals Ra and Rb.
, input terminals Ca, Cb, Db and output terminals Q0a~Q
3a, Q0b to Q2b.

The reset terminals Ra and Rb of the shift register 24 are inputted with the output of a NOR gate 36, which will be described later, and the output from the output terminal Q2 of the flip-flop circuit 9 is inputted into the NOR gate 36. When the output from the output terminal Q2 of the NOR gate 36 is L, the output becomes H, and the shift register 24 is reset. When the output from the output terminal Q2 of the flip-flop circuit 9 is H, the output of the NOR gate 36 becomes H. The output becomes L, and the reset of the shift register 24 is released. Therefore, when the shift register 23 is in the reset release state, the shift register 24
is in the reset state, and when the shift register 23 is in the reset state, the shift register 24 is in the reset state.
is set in a reset release state.

The Schmitt circuit 11 is connected to the input terminals Ca and Cb of the shift register 24 via an inverter element 37.
The output from is input. shift register 2
4 output terminals Q0a to Q3a, Q4b to Q6b
are connected to the OR circuits 29 to 35 in order, respectively, and the output from the output terminal Q3a is connected to the input terminal
Db, the output terminals Q4b to Q6b receive and output the output from the output terminal Q3a, and the output from the output terminal Q6b is fed back to the other input terminals of the OR gate 21 forming a part of the Schmitt circuit 11. has been entered.

When the output from the output terminal Q6b of the shift register 24 is L and the input terminal of the OR gate 21 is H, the output of the OR gate 21 becomes H, and the output from the output terminal Q6b of the shift register 24 becomes L. When one input terminal of the OR gate 21 is L, the output becomes L, and when the output of the output terminal Q6b of the shift register 24 is H, regardless of whether the input to the one input terminal of the OR gate 21 is L or H. The output becomes H.

ORGATE 21 is the 18th operation winning ball switch 5
When is opened and closed once, the output changes from H to L, and the output terminal Q0a of the shift register 24 changes from L to H. Along with this, the light emitting diode 8
A is now lit.

When the 18-time operation winning ball switch 5 is repeatedly opened and closed 8 times, the light emitting diodes 8a to 8g are turned on in this order. When all the light emitting diodes 8a to 8g are turned on, the output from the output terminal Q6b of the shift register 24 becomes H, and the inputs of the other input terminals of the OR gate 21 become H, so that the 18th operation winning ball switch 5 becomes 8. After opening and closing the 18-time winning ball switch 5, the output of the OR gate 21 becomes H, and the light-emitting diode group 27 is no longer lit.

The reset timing circuit 15 is the AND circuit 3
8, a NAND circuit 39, a NOR gate 40, an inverter element 41, a NOR gate 42, an AND circuit 43, and a NOR circuit 44. The AND circuit 38 includes an 8-bit binary counter circuit 1
The outputs of output terminal Q1a and output terminal Q3a of 0 are input. The output from the AND circuit 38 and the output from the output terminal Q0b of the 8-bit binary counter circuit 10 are input to the NAND circuit 39. The output from the NAND circuit 39 and the output from the OR circuit 20 are input to the NOR gate 40 . The inverter element 4 is connected to the NOR gate 42.
1, the output from the output terminal Q2b of the 8-bit binary counter circuit 10 and the output from the output terminal Q2 of the flip-flop circuit 9 are inputted. The output from the output terminal Q2b of the 8-bit binary counter circuit 10 and the output from the output terminal Q1 of the shift register 14 are input to the AND circuit 43, and the NOR gate 40 is input to the NOR circuit 44.
, the outputs of the NOR gate 42, the AND circuit 43, and the power supply voltage are input. Noah circuit 44
The output from the flip-flop circuit 9 is input to each reset terminal R0, R1, R2, and when the output from the NOR circuit 44 is L, the output from each output terminal Q0 to Q2 of the flip-flop circuit 9 is inhibited, and the NOR circuit When the output of the circuit 44 is H, the outputs from the respective output terminals Q0 to Q2 of the flip-flop circuit 9 are released. The Noah circuit 44 is
When the power supply voltage of the NOR gates 40 and 42 and the AND circuit 43 is L, the output becomes H, and the flip-flop circuit 9 is released from reset.

The AND circuit 38, the NAND circuit 39, and the NOR gate 40 are used as a reset timing circuit that operates the solenoids 2a and 2b once, and the inverter element 41 and the NOR gate 42 serve as a reset timing circuit that operates the solenoids 2a and 2b twice. The AND circuit 43 is a reset timing circuit that operates the solenoids 2a and 2b 18 times.

The output of the NOR gate 40 is always L when the outputs of the output terminals Q1 and Q2 of the flip-flop circuit 9 are H, and the output of the NOR gate 42 is always L when the output from the output terminal Q2 of the flip-flop circuit 9 is H. Its output is set to be L.

The solenoids 2a and 2b are connected to the switching circuit 4.
5 and 46, respectively, and the switching circuit 4
5 and 46 are connected to OR gates 47 and 48, respectively, and the OR gates 47 and 48 are connected to the output terminal Q0b of the 8-bit binary counter circuit 10. Therefore, the eighth clock is input to the solenoids 2a and 2b. It does not start operating until it falls (see Figure 6). The time that is eight times the clock cycle is hereinafter referred to as the "wait time." Note that in this example, the clock period is set to 0.1 seconds, so the wait time is
It will be 0.8 seconds.

Further, the output terminal Q0b of the 8-bit binary counter circuit 10 is connected to an AND circuit 49, and the NOR gate 36 and the AND circuit 49 have a function of controlling the sound effect generation circuit 18. Here, solenoids 2a and 2b are
A sound effect is generated during the 18th movement. 50 is a display circuit that indicates that the solenoids 2a and 2b are operating 18 times, and a lamp 52
and an AND circuit 53.

Next, the effect will be explained.

() The 1-time action winning ball switch 6, the 2-time action winning ball switch 7, and the 18-time action winning ball switch 5 are all open, and the inputs of the set terminals S0, S1, and S2 of the flip-flop circuit 9 are H, and the OR gate is When the input to one input terminal of 21 is H and the input to the other input terminal is L.

Output terminals Q0 to Q of flip-flop circuit 9
2 is L, and the output of OR gate 21 is H, so H is input to one input terminal of NAND gate 13, L is input to the other input terminal, and H is input from NAND gate 13. Output. Therefore, the input to the reset terminal Ra of the 8-bit binary counter circuit 10 is set to L, and the input to the reset terminal Rb of the 8-bit binary counter circuit 10 is set to H. Therefore, the 8-bit binary counter circuit 10
The reset of the reset terminal Ra is released, the output from the output terminal Q0a is released, the clock signal from the clock oscillation circuit 16 is output from the output terminal Q0a, and the light emitting diode group 27 is activated as shown in FIG. The blinking state of each diode row is repeated from the top and bottom toward the center.

On the other hand, the reset terminal Rb of the 8-bit binary counter circuit 10 is reset, output from the output terminals Q0b to Q3b is prohibited, and the solenoids 2a and 2b are not driven.

() When the one-time operation winning ball switch 6 is closed and the input to the other input terminal of the OR gate 21 is L.

Once the winning ball switch 6 is closed,
The set terminal S0 of the flip-flop circuit 9 is high.
The output from the output terminal Q0 changes from L to H. The output is inputted to the reset terminal Ra of the 8-bit binary counter circuit 10 via the delay circuit 12, and also inputted to the other input terminals of the NAND gate 13. On the other hand, the OR gate 21 is outputting H at this time, and its output is input to one input terminal of the NAND gate 13. From the NAND gate 13, the reset terminal Rb of the 8-bit binary counter circuit 10 is input.
L is input to . The input of the reset terminal Rb is the output terminal Q0 of the flip-flop circuit 9.
When the output changes from L to H, it is set to L.
When the output from the output terminal Q0 of the flip-flop circuit 9 changes from L to H, the reset terminal Ra of the 8-bit binary counter circuit 10 is reset for a time equal to the time constant by the differential circuit of the delay circuit 12, and the output from the output terminals Q0a to Q3a is reset. output is prohibited. Further, the reset terminal Rb of the 8-bit binary counter circuit 10 is connected to the delay circuit 12.
After the delay time due to the time constant of the integrating circuit has elapsed, the reset is released and a rectangular signal as shown in FIG. 5 is output from the output terminals Q0b to Q3b.

At this time, the solenoids 2a and 2b are driven after the wait time has elapsed.
The operations a and 2b operate once when a pachinko ball enters the specific winning hole, and after closing the winning ball switch 6, the operation is performed for 0.8 seconds (wait time).
Since the guide blades 1c and 1d are opened and closed once by the solenoids 2a and 2b when the time has elapsed, the player can move his line of sight from the specific winning opening to the guiding blades 1c and 1d of the winning device. Thereby, it is possible to perceive whether the pachinko ball will enter the winning device or not, and whether the pachinko ball that entered the winning device will enter the continuous winning hole.

And an AND circuit 38, a NAND circuit 39,
Due to the one-time operation reset timing circuit of the NOR gate 40, when the NAND circuit 39 outputs L, the NOR circuit 44 outputs L, and the reset terminals R0 and R of the flip-flop circuit 9
1 and R2 are reset (see FIG. 6).

Therefore, output from the output terminals Q0, Q1, and Q2 of the flip-flop circuit 9 is prohibited, and the solenoids 2a and 2b are driven for only 0.5 seconds as shown in FIG.

() 2-time operation When the winning ball switch 7 is closed and the input to the other input terminal of the OR gate 21 is L.

When the two-time operation winning ball switch 7 is closed,
The set terminal S1 of the flip-flop circuit 9 is high.
The output from the output terminal Q1 changes from L to H. The output thereof is inputted to the reset terminal Ra of the 8-bit binary counter circuit 10 via the delay circuit 12, as in the case () above, and is also inputted to the other input terminals of the NAND gate 13. On the other hand, OR gate 21 is outputting H at this time, and its output is NAND gate 1
3, and L is input from the NAND gate 13 to the reset terminal Rb of the 8-bit binary counter circuit 10. still,
At this time as well, the input to the reset terminal Rb is set to L when the output from the output terminal Q1 of the flip-flop circuit 9 changes from L to H.

When the output from the output terminal Q1 of the flip-flop circuit 9 changes from L to H, the reset terminal Ra of the 8-bit binary counter circuit 10 is reset for a time equal to the time constant by the differential circuit of the delay circuit 12, and the output from the output terminals Q0a to Q3a is reset. output is prohibited. Further, the reset terminal Rb of the 8-bit binary counter circuit 10 is released from reset, and rectangular signals as shown in FIG. 5 are output from the output terminals Q0b to Q3b.

At this time, the solenoids 2a and 2b are driven after the wait time has elapsed.
The operations of a and 2b are performed twice when a pachinko ball enters the specific winning hole.When 0.8 seconds have elapsed after the winning ball switch 7 is closed, the guide vanes 1c and 1d actuate the solenoids 2a and 2b.
Since it is opened and closed twice, the player can move his line of sight from the specific winning opening to the guide blades 1c and 1d of the winning device. Thereby, it is possible to perceive whether the pachinko ball will enter the winning device or not, and whether the pachinko ball that entered the winning device will enter the continuous winning hole.

Then, the inverter element 41 and the NOR gate 4
With the two-time operation reset timing circuit of 2,
When the NOR gate 42 outputs an H level, the NOR circuit 44 outputs an L level, and the reset terminals R0, R1, and R2 of the flip-flop circuit 9 are reset (see FIG. 7).

Therefore, output from the output terminals Q0, Q1, Q2 of the flip-flop circuit 9 is prohibited, and the solenoids 2a, 2b are driven only twice for 0.8 seconds each as shown in FIG.
As described above, the one or two operations of the guide vanes 1c and 1d are in the first state.

() 18th operation When winning ball switch 5 is closed.

When the 18th operation winning ball switch 5 is closed,
L is momentarily input to one input terminal of the OR gate 21, and at this time, the output terminal Q6b of the shift register 24 is input to the other input terminal of the OR gate 21.
L is input from the OR gate 21, and L is output from the OR gate 21. Its output is NAND gate 1
At this time, if the guide vanes 1c and 1d are in the middle of the first and second operations, H is input to the other input terminal of the NAND gate 13, so from the NAND gate 13,
A high level is momentarily output, and this output is input to the reset terminal Rb of the 8-bit binary counter circuit 10. Therefore, the reset terminal Rb is instantaneously reset, and the output from the output terminal Q0b of the 8-bit binary counter circuit 10 is prohibited. Therefore, in the middle of the first and second movements
When the 18th operation winning ball switch 5 is closed, the 1st and 2nd operation immediately ends at that point.
Further, the output from the OR gate 21 is input to the set terminal S2 of the flip-flop circuit 9.
H is output from the output terminal Q2. The output H is sent to the reset terminal Ra of the 8-bit binary counter circuit 10 via the OR circuit 20, the OR circuit 19, and the delay circuit 12, as in () and () above.
It is also input to the other input terminals of the NAND gate 13. On the other hand, at this time, the 18th operation winning ball switch 5 is open, H is input to one input terminal of the OR gate 21, H is output from the OR gate 21, and one input terminal of the NAND gate 13 is H. The L output from the NAND gate 13 is input to the reset terminal Rb of the 8-bit binary counter circuit 10.

In this case, as in () and () above, the input of the reset terminal Rb is connected to the flip-flop circuit 9.
When the output from the output terminal Q2 changes from L to H, it becomes L.

Therefore, the 8-bit binary counter circuit 10
The reset terminal Ra of is reset, and the output terminal Q
Outputs from 0a to Q3a are prohibited. Also, 8
Reset terminal of bit binary counter circuit 10
Rb is reset and output terminal Q0b~
A rectangular signal as shown in FIG. 5 is output from Q3b.

Therefore, the solenoids 2a and 2b are driven, but due to the 18-time operation reset timing circuit of the AND circuit 43, when an H is output from the AND circuit 43, an L is output from the NOR circuit 44, and the flip-flop circuit 9 Reset terminals R0, R1,
R2 is reset (see Figure 8).

Therefore, output from the output terminals Q0, Q1, and Q2 of the flip-flop circuit 9 is prohibited, and the solenoids 2a and 2b are driven 18 times for 0.8 seconds each as shown in FIG. In this way, the 18 opening and closing operations of the guide members 1c and 1d are in the second state.

In addition, during the 18th operation of the guide blades 1c and 1d, the output of the OR circuit 19 is H, and even if there is a win in the 1st or 2nd operation to the specific winning opening during the 18th operation, the OR circuit will not be activated. The output of 19 remains at H and does not change, so the binary counter circuit 10 is not reset, and the winnings between the 1st and 2nd actions by the 1st action winning ball switch 6 and the 2nd action winning ball switch 7 are not reset. The signal is ignored and the operation continues 18 times.

Since the output from the NOR circuit 44 is input to the reset terminals R0, R1, and R2 of the flip-flop circuit 9, the output from the specific winning opening is 18 times during the 18th operation.
Even if there is a winning prize for the 18th and 2nd operation, the output terminal Q of the flip-flop circuit 9 will be
Since 0, Q1, and Q2 are all reset, after the 18th operation is completed, the 1st and 2nd operations will not be performed due to the winning of the 1st and 2nd operations during the relevant operation.

In addition, when the 18th operation winning ball switch 5 is closed again while the solenoids 2a and 2b are being driven,
L is momentarily input to the input terminal of the OR gate 21 upon closing of the 18-time winning ball switch 5, and L is momentarily outputted from the OR gate 21 accordingly. The output is input to one input terminal of the NAND gate 13, and at this time, since H is input to the other input terminal of the NAND gate 13, H is momentarily output from the NAND gate 13, and the output is 8 bits. Binary counter circuit 1
0 reset terminal Rb. Therefore,
The reset terminal Rb is momentarily reset, and the output terminal Q0b of the 8-bit binary counter circuit 10 is reset.
output is momentarily inhibited (see Figure 9).

Therefore, 8-bit binary counter circuit 1
The 18-time operation rectangular signal from output terminal Q0b of
As shown in FIG. 9, the process starts again from the beginning.

When the 18th operation winning ball switch 5 is closed,
H from output terminal Q2 of flip-flop circuit 9
The output is further input to the reset terminal R of the shift register 23 and to the NOR gate 36. Therefore, the output from the set terminals S0 to Q3 of the shift register 23 is prohibited, and the light emitting diodes 8a to 8g are all turned off, while L is output from the NOR gate 36, and the output is sent to the reset terminals Ra and Q3 of the shift register 24. The signal is input to Rb, and the reset terminals Ra and Rb are released from reset. At this time, the input terminal of the shift register 24
For Ca and Cb, 18
The output from the OR gate 21 accompanying the closing of the rotary winning ball switch 5 is input, and the output terminal Q0a of the shift register 24 outputs H. Along with this, the light emitting diode 8a is turned on. Similarly, 18 of solenoids 2a and 2b
18 times during the rotation, the winning ball switch 5 repeats 8
When the light emitting diode 8b is opened and closed twice, the light emitting diode 8b
~8g is lit.

When all the light emitting diodes 8a to 8g are turned on, H is output from the output terminal Q6b of the shift register 24, and the inputs of the other input terminals of the OR gate 21 are set to H. Therefore, after the 18-time winning ball switch 5 opens and closes 8 times, the output of the OR gate 21 becomes H regardless of whether the 18-time winning ball switch 5 is opened or closed, and the light emitting diode group 27 does not light up after that. do not have.

In addition, in the winning probability increase state, if the winning ball switch 5 does not win the winning ball, the winning ball switch 5 operates 18 times, and as described above, the guide blade moves once and twice, and although it ends after the 18th movement, the winning ball enters the winning area of the winning device. The game may end when a predetermined number of pachinko balls (for example, 10 balls) win.

(Effects of the Invention) As is clear from the above description, the present invention provides a pachinko machine in which the opening and closing of a movable piece based on a winning of a specific winning opening and the continuous updating of rights advantageous to the player can be perceived. can be provided. This allows the player to visually see whether or not advantageous rights will continue to occur, increasing expectations and changes in the game. Furthermore, since the start and end of rights advantageous to the player are made clear and the rights can be effectively utilized, the player's desire to play increases. In addition, the player can reliably sense whether the movable piece has opened or closed based on the winning of the specific winning opening, and the player's confidence in the Pachinko machine can be increased.

[Brief explanation of drawings]

FIG. 1 is a schematic front view showing one embodiment of the present invention, FIG. 2 is a schematic perspective view showing one embodiment of the present invention, FIG. 3 is a control diagram used in the present invention, and FIG.
5 is a signal waveform diagram of the clock signal output from the 8-bit binary counter circuit, FIG. 6 is a series of signal waveform diagrams when the solenoid is made to open and close once, and FIG. , a series of signal waveform diagrams when the solenoid is made to open and close twice, Figure 8 is a series of signal waveform diagrams when the solenoid is made to open and close 18 times, and Figure 9 is a series of signal waveform diagrams when the solenoid opens and closes 18 times. It is a series of signal waveform diagrams when the 18-time operation winning ball switch is closed during operation. 1... Winning device, 1c, 1d... Movable piece (guide vane), 2a, 2b... Electric drive unit (solenoid), 4... Continuous winning opening, 9, 11, 12, 13,
15... Drive circuit (flip-flop circuit, Schmitt circuit, delay circuit, reset release control circuit,
10...operation circuit (8-bit binary counter circuit).

Claims (1)

[Scope of Claims] 1. A game board from which pachinko balls are shot is provided with a specific winning hole and a winning device, and the winning device includes a continuous winning hole, a movable piece that can be opened and closed with respect to the winning device, and the movable piece. A pachinko machine is provided with an electric drive unit that drives the pieces to open and close, and a drive circuit that generates a drive signal for the electric drive unit based on a win in the specific winning opening or continuous winning opening, A pachinko machine characterized by being provided with an operation circuit for controlling a drive circuit that generates a drive signal when a preset wait time has elapsed.