JPH0221887A - Japanese pinball game (pachinko) machine - Google Patents

Abstract

PURPOSE:To visually confirm the opening and closing of movable pieces when the player observes the movable pieces simply before a previously set waiting time lapsing, by providing an actuation circuit for controlling a drive circuit, which delivers a drive signal when the waiting time lapses from the time of prize wining at a specific prize wining port. CONSTITUTION:Guide blades 1c, 1d as movable pieces which are opened and closed about pivotal shafts 1a, 1b in directions in which pinballs are trapped, are provided in the center part of a prize wining device 1, and are connected to rods 2c, 2d constituting parts of solenoids 2a, 2b as electrical drive sections which are energized after a waiting time lapsing. The guide blades 1c, 1d are opened and closed by one cycle time by means of the solenoids 2a, 2b after 0.8sec (waiting time) lapsing from the time when a one prize wining pinball switch 6 is closed in association with introduction of a pinball into a specific prize wining port, and accordingly, the player shifts his sight from the specific prize wining port to the guide blades 1c, 1d of the prize wining device. Thereby it is possible to visually confirm whether a pinball is introduced into the prize wining device or not, and whether a pinball introduced into the prize wining device is introduced into a successive prize wining port or not.

Description

Detailed Description of the Invention (Industrial Application Field) The present invention, when a pachinko ball flies into a continuous winning opening, starts to maintain a state that increases the winning probability of a winning device within a predetermined time, and To provide a pachinko machine which starts the winning probability increasing state again from the beginning when a pachinko ball flies into the continuous winning hole again during the winning probability increasing state of the device.

(Prior Art) Conventionally, some pachinko machines increase the winning probability of a winning device using winning balls. This type of pachinko machine has a specific winning hole and a winning device arranged on the game board from which pachinko balls are shot, and this winning device has a continuous winning hole and a movable piece that can be opened and closed with respect to the winning device, and this movable piece. It is provided with an electric drive section that drives the opening and closing of the electric drive section, and a drive circuit that generates a drive signal for the electric drive section. The specific winning hole and the continuous winning hole are for increasing the winning probability, and when a pachinko ball enters the specific winning hole, the drive circuit generates a drive signal. Then, based on the generation of this drive signal, the electric drive section opens and closes the movable piece once or twice, making it easier for the pachinko ball to enter the winning device and increasing the winning probability.

When the winning probability increases, when the pachinko ball enters the winning device and further enters the continuous winning slot, the drive circuit generates a drive signal different from that when winning a specific winning slot, and generates this drive signal. Based on this, the electric drive opens and closes the movable piece 18 times. Therefore, the winning device continuously increases the winning probability of the pachinko balls, and the player continues to receive advantageous rights. In addition, if a prize is entered into the continuous winning slot again while the movable piece has been opened and closed 18 times, the right will be renewed and the 18th opening and closing of the movable piece will start from the beginning, and this renewal will be repeated 8 times. will continue until

When playing a pachinko game using such a pachinko machine, the player increases the possibility that the movable piece will open and close once or twice by aiming at a specific winning opening during a normal game.

As a result, the player can increase the probability that more pachinko balls will enter the winning device and also enter the continuous winning slot, so that rights advantageous to the player will continue to occur. In addition, if a player wins a prize in prize bag a while the movable piece is opening and closing once or twice, and furthermore wins in the continuation prize slot, in order to effectively utilize the rights advantageous to the player, the player To aim a movable piece so that a pachinko ball can most easily enter a prize in a winning device. As a result, a larger number of prize balls can be expected to be paid out compared to the normal game.

In addition, the time required to open and close the movable piece based on a winning of a specific winning opening is set to be about 0.5 seconds in the case of 1 time, and about 0.8 seconds each time in the case of 2 times and 18 times. ing. In addition, the winning probability in such a pachinko machine has been increased by generating a driving signal immediately after the drive circuit wins a prize in a specific winning hole or a continuous winning hole.

(Problem to be Solved by the Invention) However, during normal gaming, the player is aiming at a specific winning opening, so the winning state of the specific person's π opening is visually observed, and the winning device is not visible to the player. It's out of place.

In addition, the opening and closing of the movable piece based on the winning of the specific winning opening is 0.
Since it is about 5 seconds or 0.8 seconds, if you are aiming at a specific winning opening, you may miss the opening and closing of the movable piece based on the winning of the specific winning opening. In this case, the player cannot visually see whether the pachinko ball will enter the winning machine or not, and if the pachinko ball enters the winning machine, whether it will enter the continuous winning slot.In other words, it is advantageous to the player. Since it is not possible to visually check whether or not a certain right will continue to occur, there is a problem in that expectations and changes in the game are reduced.

Therefore, an object of the present invention is to provide a pachinko machine in which opening/closing and updating of a movable piece can be perceived based on a winning of a specific winning opening.

(Means for Solving the Problems) Therefore, in order to solve such problems, the present invention provides drive circuit control that generates a drive signal when a preset wait time has elapsed from the time of winning a prize in a specific winning opening. The configuration includes an operating circuit for

(Function) Since the present invention is configured as described above, the drive circuit causes the operation circuit to generate a drive signal after the wait time has elapsed since the pachinko ball entered the specific winning hole. Thereby, if a pachinko ball enters a specific winning hole and the player visually observes the movable piece before the waiting time elapses, he or she can perceive whether the movable piece is opened or closed.

(Example) An embodiment of the present invention will be described below.

In FIG. 1, 1 is a winning device according to the present invention, and in the center of this winning bag 2i, starting from pivots 1a and lb,
Guide vanes 1c and ld are provided as movable pieces that open in the direction of picking up pachinko balls. That is, the guide vane 1c rotates counterclockwise until it becomes as horizontal as possible, and the guide vane 1d rotates clockwise until it becomes as horizontal as possible. The guide vanes 1c, ld are linked with rods 2e, 2d forming part of solenoids 2a, 2b as electric drive units, as shown in FIG. Guide vane 1
c.

1d is opened when the solenoids 2a and 2b are driven. At the bottom of the winning device l, partition plates 3, 3 are set up, and between the partition plates 3, 3 is a continuous winning opening 4, and this continuous winning opening 4 is equipped with a continuous winning detector 188. A 188 rotation winning ball switch 5 is provided for rotating the ball. In addition to this, two other specific winning openings (paths shown) are provided, and the other - specific winning opening operates once as a specific winning detector, as shown in Figure 3. 1 to make it happen
A rotating winning ball switch 6 is provided, and a two-time winning ball switch 7 is provided in the other two specific winning holes to operate twice as a specific winning detector, as shown in FIG. It is provided. On the front surface of the winning device M1, light emitting diodes 8a to 8g are arranged as part of the notification means.

FIG. 3 shows a drive circuit for the solenoids 2a and 2b, which includes a flip-flop circuit 9, an 8-bit binary counter circuit 10, a Schmitt circuit 11, a delay circuit 12, . Reset release drive circuit 13, shift register 14 as an operation circuit, and reset timing circuit 1
5 is the main configuration. Further, 16 is a clock oscillation circuit, 1
7 is a light emitting diode blinking circuit as a notification means, and 18 is a sound effect generation circuit as a notification means.

The configuration and function of each of these circuits will be explained below.

The flip-flop circuit 9 has a set terminal 5O9S L,
S2. S3, and output terminals QO, Ql, Q2.
Q3, reset terminals RO, R1, R2, R3, and a ground terminal EO.
, reset terminal R3, and output terminal Q3 are not used.

The power supply voltage VDD is connected to the set terminals SO,
SL and the Schmitt circuit 11. The power supply voltage VDD is on the high potential side, and each switch 6.7.5
However, when it is in the open state as shown in FIG. 3, the set terminals So, Sl, and S2 are at H input. Set terminal SO changes from H to L when switch 6 is closed, set terminal S1 changes from H to L when switch 7 closes, and set terminal S2 changes from H to L when switch 7 is closed. When grown, it becomes H mustard. Each of the output terminals QO to Q2 is set to an L output when each of the set terminals SO to S2 is H, and is set to an H output when each of the set terminals SO to S2 is set to L. 19.20 is an OR circuit. The OR circuit 19 is connected to the output terminal QO of the flip-flop 9.
- Outputs H when at least one of Q2 is H,
The OR circuit 20 is connected to either one of the output terminals QO, Q2 or H
These OR circuits 19 and 20 have the function of inhibiting the output of each component of the reset timing circuit 15. The Schmitt circuit 11 has an OR gate 21, and a reset release control circuit 1 that controls the 8-bit high-power counter circuit 10.
3 is composed of a Nant gate, and one input terminal of the Nant gate 13 receives the output of the Schmitt circuit 11.
The output of the OR circuit 19 is input to the other input terminal of the Nant gate 13 via the delay circuit 12. The delay circuit 12 is composed of a group of resistance capacitors, and the function of this delay circuit 12 is that of an 8-bit binary counter circuit I.
This will be explained together with the configuration of O.

The 8-bit binary counter circuit 10 has a reset terminal R.
a, Rb, and output terminals QOa to Q3a, QOb to Q3b
and input terminals E a and E b. The input terminal Ea is connected to a clock oscillation circuit 16 that generates a lock signal as shown in FIG.
a to Q3a are designed to generate rectangular signals as shown in FIG.

The output terminal QOa has a period twice the period of the clock signal and has a function of outputting when the first clock signal is input, and the output terminal Qla has a period four times the period of the clock signal. It has a period and has a function of outputting when the second clock signal is input, and the output terminal Q2a is
The output terminal Q3a has a cycle that is 8 times the cycle of the clock signal, and has a function of outputting when the fourth clock signal is input, and the output terminal Q3a has a cycle that is 16 times the cycle of the clock signal. It has a function of outputting when the eighth clock signal is input.

The output of the output terminal Q3a is input to the input terminal Eb, and the output terminal QOb is connected to the output terminal Q as shown in FIG.
It has twice the cycle of the rectangular signal from output terminal Q3a, and when the first output signal of the rectangular signal from output terminal Q3a, that is, the eighth clock signal, is input and falls, the output H rises. It has a function (see Figure 6)
, and the output terminal Qlb is not used here, and the output terminal Q2b has a period eight times that of the rectangular signal from the output terminal Q3a, and the fourth of the rectangular signals from the output terminal Q3a. The output terminal Q3b has a period 16 times that of the rectangular signal from the output terminal Q3a, and the 8th output signal from the output terminal Q3a The output of the output terminal Q3b is sent to the input terminal C of the shift register 14 via the inverter element 22.
It is input to P.

The shift register 14 has the input terminal CP, a reset terminal R1, a power supply potential terminal D, and output terminals QO, Ql, and Q2. The other is connected to the power supply VDD.

As shown in FIG. 5, the output terminal QO of the shift register 14 has a period 32 times that of the rectangular signal from the output terminal Q3a, and the 16th rectangular signal from the output terminal Q3a is input. The output terminal Q1 has a period that is 64 times that of the rectangular signal from the output terminal Q3a, and is not used here.
It has a function of outputting when the 32nd rectangular signal from the output terminal Q3a is input, and the output terminal Q2 is not used here.

Reset terminal Ra of 8-bit binary counter circuit 10
is connected to the delay circuit 12, and the output from the OR circuit 19 is delayed by 0.5 seconds and then sent to the reset terminal Ra.
It is now entered into This reset terminal Ra
is for releasing the output from the output terminal QOa when its input is low, and inhibits the output of QOa when its input is high.

The output of the Nandt gate 13 is input to the reset terminal Rb of the 8-bit binary counter circuit IO,
When the input of the reset terminal Rb is H, the output terminal QOb
Output from the output terminal QOb is prohibited, and when the input to the reset terminal Rb is L, the output from the output terminal QOb is released.

The input to the reset terminal Rb is the reset terminal Ra.
When the input becomes H, the signal becomes L at the same time.

The light emitting diode blinking circuit 17 is roughly composed of two shift registers 23 and 24, an OR circuit group 25, a light emitting diode drive circuit 26, and a light emitting diode group 27.

The shift register 23 has an input terminal CP, a reset terminal R, and output terminals QO to Q3, and the output from the output terminal Q2 of the flip-flop circuit 9 is input to the input terminal CP. The output from the output terminal QOa of the 8-bit binary counter circuit IO is input.

The outputs from the output terminals QO to Q3 of the shift register 23 are fed back to the input terminals of the shift register 23 via the NOR circuit 28, and the output from the output terminal QO is fed back to the OR circuit 29.
The output from the output terminal Q1 is input to the OR circuit 30 and the OR circuit 34, the output from the output terminal Q2 is input to the OR circuit 31 and the OR circuit 33, and the output from the output terminal Q3 is input to the OR circuit 31 and the OR circuit 35. The output from is input to the OR circuit 32.

The light emitting tie auto drive circuit 26 has input terminals IO to I6 and output terminals QO to Q6, the OR circuit 29 controls the output from the output terminal QO, and the OR circuit 30 controls the output from the output terminal Ql. It controls the output from
The OR circuit 31 controls the output from the output terminal Q2, the OR circuit 32 controls the output from the output terminal Q3, and the OR circuit 33 controls the output from the output terminal Q4. , the OR circuit 34 is connected to the output terminal Q5
The OR circuit 35 controls the output from the output terminal Q6, and the light emitting diodes 8a and 8g are connected to the output terminal Q of the shift register 23.
Blinking is controlled by the output from O, and the light emitting diode 8b
, 8f are controlled to blink by the output from the output terminal Ql of the shift register 23, the light emitting diodes 8c and 8e are controlled to blink by the output from the output terminal Q2 of the shift register 23, and the light emitting diode 8d is controlled by the output from the output terminal Q2 of the shift register 23.
The light emitting diode group 27 is controlled to blink by the output from the output terminal Q3, and the light emitting diode group 27 is made to blink from the top and bottom of each diode row toward the center as shown in FIG. Each diode row has a Ja spear that repeats the blinking state from the beginning from the top to the center after the blinking state is completed.

In addition, when the input of the reset terminal R of the shift register 23 is H, the reset terminal R of the shift register 23 is connected to the output terminals QO to Q of the shift register 23.
The light emitting diode group 27 has a function of inhibiting the output from the output terminal Q2 of the flip-flop circuit 9.
When the output from is H, all lights are turned off.

The shift 1 register 24 has reset terminals Ra, Rb,
Input terminals Ca, Cb, Db and output terminals QOa to Q3
a, Q Ob to Q 2b.

The reset terminals Ra and Rb of the shift register 24 are input with the output of a NOR gate 36, which will be described later.
The output from 2 is input. When the output of this output terminal Q2 is L, the output of the NOR gate 36 becomes H.
The shift register 24 is reset, and when the output from the output terminal Q2 of the flip-flop circuit 9 is H, the output of the NOR gate 36 becomes L, and the shift register 24 is released from reset. . Therefore, when the shift register 23 is in the reset release state, the shift register 24 is in the reset state,
When the shift register 23 is in the reset state, the shift register 24 is in the reset release state.

The output from the Schmitt circuit 11 is input to input terminals Ca and Cb of the shift register 24 via an inverter element 37. Output terminal Q O of shift register 24
a to Q3a, Q4b to Q6b are connected to OR circuits 29 to 35 in order, respectively, and output terminals Q
The output from the output terminal Q6b is fed back to the input terminal Db, and the output terminals Q4b to Q6b receive and output the output from the output terminal Q3a, and the output from the output terminal Q6b constitutes a part of the Schmitt circuit 11. is input to the value input terminal of the OR gate 21.

The OR gate z1 is connected to the output terminal Q6 of the shift register 24.
When the output from Q6b is on and the input terminal of the OR gate 21 is H, the 5 output becomes H, and the output from the output terminal Q6b of the shift register 24 is on and one input terminal of the OR gate 21 When the output of the output terminal Q6b of the shift register 24 is H, the output becomes H regardless of whether the input to one input terminal of the OR gate 21 is L or H.

When the OR gate 21 operates 18 times and the winning ball switch 5 is opened and closed once, the output changes from H to L, and the output terminal QOa of the shift register 24 changes from L to H. Along with this, the light emitting diode 8a is turned on.

When the 18-time operation winning ball switch 5 is repeatedly opened and closed 8 times, the light emitting diodes 88 to 8g are turned on in this order. When all the light emitting diodes 8a to 8g are lit, the output from the output terminal Q6b of the shift register 24 becomes H, and the human power at the value input terminal of the OR gate 21 becomes H, so the winning ball switch 5 or 8 operates 18 times. After opening and closing 18 times, the output of the or game 1-21 becomes H and the lighting of the 1 light emitting diode group 27 is prevented thereafter, regardless of whether the winning ball switch 5 operates 18 times.

The reset timing circuit 15 includes an AND circuit 38, a NAND circuit 39, a NOR gate 40, and an inverter element 4.
1, a NOR gate 2, an AND circuit 43, and a NOR circuit 44. The AND circuit 38 includes the output terminal Qla of the 8-bit binary counter circuit 10 and the output terminal Q3.
The output of a is input. The output from the AND circuit 38 and the output from the output terminal QOb of the 8-bit binary counter circuit 10 are input to the NAND circuit 39 . The output from the NAND circuit 39 and the output from the OR circuit 20 are input to the NOR gate 40 . The output from the output terminal Q2b of the 8-bit binary counter circuit 10 and the output from the output terminal Q2 of the flip-flop circuit 9 are input to the NOR gate 42 via the inverter element 41. The output from the output terminal Q2b of the 8-bit binary counter circuit 10 and the output from the output terminal Ql of the shift register 14 are input to the AND circuit 43, and the NOR gate 40 and the NOR gate 40 are input to the NOR circuit 44.
12, each output of the ant circuit 43, and a power supply voltage are input. The output from the NOR circuit 44 is provided to each reset terminal RO of the flip-flop circuit 9.

R1 and R2, and when the output from the NOR circuit 44 is L, each output terminal QO of the flip-flop circuit 9
The outputs of Q2 to Q2 are prohibited, and when the output of the NOR circuit 44 is H, the outputs from the output terminals QO to Q2 of the flip-flop circuit 9 are released. The NOR circuit 44 has an output of H when the NOR gates 40, 42, AND circuit 43, and the power supply voltage are L, and the flip-flop circuit 9 is reset or released.

The AND circuit 38, the NAND circuit 39, and the NOR gate 40 are used as a reset timing circuit that operates the solenoids 2a and 2b once, and the inverter element 41 and the NOR gate 42 operate the solenoids 2a and 2b once.

The AND circuit 43 is a reset timing circuit that operates the solenoid 2a twice.

It is said to be a reset timing circuit that rotates 2b 188 times.

The output of the NOR gate 40 is always L when the outputs of the output terminals Ql and Q2 of the flip-flop circuit 9 are H, and the NOR gate 42 outputs the output from the output terminal Q2 of the flip-flop circuit 9 when the output is H. , its output is determined to be L.

Solenoids 2a and 2b are switching circuits 45°4
The switching circuits 45 and 46 are respectively connected to the OR gates 47 and 48, and the OR gates 47 and 4 are connected to the OR gates 47 and 4, respectively.
8 is the output terminal QO of the 8-bit binary counter circuit IO
connected to b. For this reason, the solenoids 2a, 2
b does not operate until the eighth clock is input and falls (see FIG. 6). The time that is eight times the clock cycle is hereinafter referred to as "wait time." In this embodiment, the clock period is set to 0.1 seconds, and therefore the wait time is 0.8 seconds.

Also, the output terminal Q of the 8-bit binary counter circuit 10
Ob is connected to an AND circuit 49, and the Noah gate 36 and the AND circuit 49 have a function of controlling the effect generation circuit 18. A sound effect is generated while rotating. 50 is the solenoid 2a, 2b
is a display circuit that displays that the is rotating 188 times,
It is roughly composed of a lamp 52 and an ant circuit 53.

Next, the effect will be explained.

(i) The one-time winning ball switch 6, the twice-playing winning ball switch 7, and the 188-time winning ball switch 5 are all open, and the set terminals S O, S of the flip-flop circuit 9 are open.
1. When the input of S2 is H, and the input of one input terminal of the OR gate 21 is H1 and the input of the other input terminal is L.

The outputs of the output terminals QO to Q2 of the flip-flop circuit 9 are L, and the output of the OR gate 21 is H, so an H is input to one input terminal of the Nant gate 13, and measles is input to the other input terminal. Then, H is output from the Nant gate 13. Therefore, the input to the reset terminal Ra of the 8-bit binary counter circuit 10 is set to L.
Reset terminal Rh of 8-hit binary force counter circuit 10
The input of is set to H. Therefore, the reset of the reset terminal Ra of the 8-bit binary counter circuit 10 is released, the output from the output terminal QOa is released, and the clock signal from the clock oscillation circuit 16 is output from the output terminal QOa, and the light emitting diode Group 27 is the first
As shown in the figure, the blinking state is repeated from the top and bottom of each diode row toward the center.

On the other hand, the reset terminal Rb of the 8-bit binary counter circuit 10 is reset, and the output terminal QOb-Q3b
Output from solenoids 2a and 2b is prohibited.
is in a non-driven state.

(ii) One-time operation winning ball switch 6 is closed.

When the input to the value input terminal of OR gate 21 is low.

Once the winning ball switch 6 is closed.

The set terminal SO of the flip-flop circuit 9 is changed from H to L, and the output from the output terminal QO is changed from H to H. The output thereof is input to the reset terminal Ra of the 8-bit binary counter circuit 10 via the delay circuit 12 and to the value input terminal of the Nandt gate 13. On the other hand, the OR gate 21 is outputting H at this time, and its output is input to one input terminal of the Nantes gate 13. It is input only to terminal Rb. Note that the input to the reset terminal Rb is set to L when the output from the output terminal QO of the flip-flop circuit 9 becomes H. When the output from the output terminal QO of the flip-flop circuit 9 changes from L to H, the reset terminal Ra of the 8-pin 1-binary counter circuit 10 is reset for a time equal to the time constant by the differential circuit of the delay circuit 12, and the output terminal QOa-Q
Output from 3a is prohibited. Further, the reset terminal Rb of the 8-bit binary counter circuit IO is connected to the delay circuit 12.
After the delay time due to the time constant of the integrating circuit has elapsed, the reset is released, and a rectangular signal as shown in FIG. 5 is output from the output terminals QOb to Q3b.

At this time, the solenoids 2a and 2b are driven after the wait time has elapsed, but the operation of the solenoids 2a and 2b is performed once after the pachinko ball enters the specific winning hole and the winning ball switch 6 is closed. , 0.8 seconds (
When the wait time) has elapsed, the solenoids 2a and 2b open and close the guide blades 1c and ld once, so the player directs his/her line of sight from the specific winning opening to the guiding blade 1c of the winning device.
, you can move it to ld. Thereby, it is possible to perceive whether the pachinko ball will enter the winning device or not, and whether the pachinko ball that entered the winning device will enter the continuous winning hole.

Then, when the NAND circuit 39 outputs L due to the one-time reset timing circuit of the AND circuit 38, the NAND circuit 39, and the NOR gate 40, the NOR circuit 44 outputs L, and the reset terminal RO of the flip-flop circuit 9 , R1, and R2 are reset (see FIG. 6).

Therefore, the output terminal QO of the flip-flop circuit 9,
Outputs from Ql and Q2 are prohibited, and solenoids 2a and 2b are driven for 0.5 seconds as shown in FIG.

(iii) When the twice-operated winning ball switch 7 is closed and the input to the value input terminal of (or game) -21 is L.

When the double-operation winning ball switch 7 is closed, the set terminal S1 of the flip-flop circuit 9 is changed from H to L, and the output from the output terminal Q1 is changed from H to H. Its output is
As in the case (ii) above, the signal is input to the reset terminal Ra of the 8-bit binary counter circuit 10 via the delay circuit 12, and is also input to the value input terminal of the Nant gate 13. On the other hand, the OR gate 21 is outputting H at this time, and its output is input to one input terminal of the NAND gate 13, and from the NAND gate 13, it is input only to the reset terminal Rh of the 8-bit binary counter circuit IO. be done. At this time as well, the power at the reset terminal Rb is set to L when the output from the output terminal Q1 of the flip-flop circuit 9 changes from L to H.

Is the output from the output terminal Ql of the flip-flop circuit 9 low?
When the signal becomes H, the reset terminal Ra of the 8-bit binary counter circuit 1O is reset for a time equal to the time constant by the differential circuit of the delay circuit 12, and output from the output terminals QOa to Q3a is prohibited. Further, the reset terminal Rb of the 8-bit binary counter circuit 10 is released from reset, and a rectangular signal as shown in FIG. 5 is output from the output terminals QOb-Q3b.

At this time, the solenoids 2a and 2b are driven after the wait time has elapsed, but the operation of the solenoids 2a and 2b is performed twice after the pachinko ball enters the specific winning hole and the winning ball switch 7 is closed. , when 0.8 seconds have elapsed, guide vanes lc and ld are solenoid 2a,
2b, the player can move his line of sight from the specific winning opening to the guide blades 1c and ld of the winning device. Thereby, it is possible to perceive whether or not the pachinko ball will enter the winning device, and whether the pachinko ball that entered the winning device will enter the continuous winning hole.

Then, when the NOR gate 42 outputs H due to the two-time operation reset timing circuit of the inverter element 41 and the NOR gate 42, the NOR circuit 44 outputs measles, and the flip-flop circuit 9 reset terminals RO, R1,
R2 is reset (see Figure 7).

Therefore, the output terminal QO of the flip-flop circuit 9,
The outputs from Ql and Q2 are prohibited, and the solenoids 2a and 2b are driven twice for 0.8 seconds each as shown in FIG. To the north, the guide vanes 1c and ld operate once or twice in the first state.

(iv) When the 188 rotation winning ball switch 5 is closed.

When the 188 rotary winning ball switch 5 is closed, the input is only momentary to one input terminal of the OR gate 21, and at this time, the shift register 2 is input to the other input terminal of the OR gate 21.
The signal is input only from the output terminal Q6b of 4, and L is output from the OR gate 21. The output is input to one input terminal of the Nantes gate I3, and at this time, the guide vane 1c
, If the ld is in the middle of the 1st and 2nd operation, H is being input to the other input terminals of the Nant gate 13, so the Nant gate 13 momentarily outputs H, and its output is 8 bits. It is input to the reset terminal Rb of the binary counter circuit IO. Therefore, the reset terminal Rh is instantaneously reset, and the output from the output terminal QOb of the 8-bit binary counter circuit 10 is prohibited. therefore,
188 rotation winning ball switch 5 in the middle of the 1st and 2nd movement
When the first and second operations are closed, at that point the 1st and 2nd operations immediately end. Further, the output from the OR gate 21 is input to the set terminal S2 of the flip-flop circuit 9, and an H level is output from the output terminal Q2. The output H is transmitted through the OR circuit 20, the OR circuit 19, and the delay circuit 12 as described above (ii
)(iii) Similarly, 8-bit binary counter circuit IO
is input to the reset terminal Ra of the Nantes gate 1.
3 is input to the other input terminal. -In this case, 1
The 88 rotating winning ball switch 5 is open, H is input to one input terminal of the OR gate 21, H is output from the OR gate 21, and one input terminal of the Nantes gate 13 is set to H. The L output from Nantes Gate 13 is 8.
It is input to the reset terminal Rb of the bit binary counter circuit 10.

In this case, as in (ii) and (iii) above, the input to the reset terminal Rb is set to L when the output from the output terminal Q2 of the flip-flop circuit 9 changes from L to H.

Therefore, the reset terminal Ra of the 8-bit binary counter circuit IO is reset, and output from the output terminals QQa to Q3a is prohibited. Further, the reset terminal Rb of the 8-bit binary counter circuit 10 is reset or released, and a rectangular signal as shown in FIG. 5 is output from the output terminals QOb to Q3b.

Therefore, when the solenoids 2a and Zb are driven or the 188 rotation reset timing circuit of the AND circuit 43 outputs an H level from the 4 AND circuits, the NOR circuit 44 outputs an L level, and the flip-flop Reset terminal RO of circuit 9.

R1 and R2 are reset (see FIG. 8).

Therefore, the output terminal QO of the flip-flop circuit 9,
Outputs from Ql and Q2 are prohibited, and solenoids 2a and 2b are driven 18 times for 0.8 seconds each, as shown in FIG. In this way, the guide member 1c,
The 18th opening/closing operation of ld is the second state.

In addition, during the 188 rotations of the guide blades 1c and ld, the output of the OR circuit 19 is H, and even if a prize is won in the specific winning opening once or twice during the 188 rotations, the OR circuit 19
The output remains at H and does not change, so the binary counter circuit 1G is not reset, and the signals caused by the winnings between the 1st and 2nd actions by the 1st action winning ball switch 6 and the 2nd action winning ball switch 7 are ignored. 188 rotations continue.

Since the output from the NOR circuit 44 is input to the reset terminals RO, R1, and R2 of the flip-flop circuit 9, even if there is a win in the 1st and 2nd operation by the specific winning opening during 188 rotations, At the end of 188 rotations, the output terminals QO, Ql, and Q2 of the flip-flop circuit 9 are all reset, so after the completion of 188 rotations, the 1st and 2nd operations due to the winnings of the 1st and 2nd operations during the operation will be canceled. Not done.

In addition, when the 188-turn winning ball switch 5 is closed again while the solenoids 2a and 2b are being driven, the input terminal of the OR gate 21 is only momentarily supplied with the opening of the 188-turn winning ball switch 5. The signal is input, and the OR gate 21 momentarily outputs L in response. The output is input to one input terminal of the Nandos game)-13, and at this time, since an H signal is input to the other input terminal of the Nands gate 13, an H signal is instantaneously output from the Nands gate 13. Its output is input to the reset terminal Rb of the 8-bit binary counter circuit IO.

Therefore, the reset terminal Rb is momentarily reset,
Output from the output terminal QOb of the 8-bit binary counter circuit IO is momentarily inhibited (see FIG. 9).

Therefore, the 188 rotation rectangular signal from the output terminal QOb of the 8-bit binary counter circuit 10 is restarted from the beginning, as shown in FIG.

When the 188 rotation winning ball switch 5 is closed, the H output from the output terminal Q2 of the flip-flop circuit 9 is further input to the reset terminal R of the shift register 23 and to the NOR gate roller. Therefore, the output from the set terminals SO to Q3 of the shift register 23 is prohibited, and the light emitting diodes 8a to 8g are all turned off, while the NOR gate 36 outputs L, and the output is sent to the reset terminal Ra of the shift register 24.

The signal is input to Rb, and the reset terminals Ra and Rb are released from reset. At this time, input terminals Ca and Cb of the shift register 24 are connected to 1
OR gate 21 due to closing of 88 rotation winning ball switch 5
The output from shift register 2 will be input.
H is output from the output terminal QOa of No. 4. Along with this, the light emitting diode 8a is also turned on. Similarly, when the 188-turn winning ball switch 5 is repeatedly opened and closed 8 times during the 188-turn of the solenoids 2a and 2b, the light emitting diodes 8b to 8g are lit in this order.

When all the light emitting diodes 88 to 8g are lit, an H level is output from the output terminal Q6b of the shift register 24,
The inputs of the other input terminals of the OR gate 2I are set to H. Therefore, after the 188 rotation winning ball switch 5 is opened and closed 8 times, the output of the or game)-21 is set to H regardless of whether the 188 rotation winning ball switch 5 is opened or closed, and the light emitting diode group 27 is turned on after that. Not done.

In addition, in the entry probability increasing state, if the 188-turn winning ball switch 5 does not win, the guide blade moves once and twice as described above, and it ends with 188 turns, but it does not enter the winning area of the winning device. The game may end when a predetermined number of pachinko balls (for example, 10 balls) win.

(Effects of the Invention) As is clear from the above description, the present invention enables a perceptible pachinko machine to open and close a movable piece based on a winning of a specific winning opening, and to continuously renew rights advantageous to the player. can be provided. This allows the player to visually see whether or not advantageous rights will continue to occur, increasing expectations and changes in the game. Furthermore, since the start and end of rights advantageous to the player are made clear and the rights can be effectively utilized, the player's desire to play increases. In addition, the player can reliably sense whether the movable piece has been opened or closed based on the winning of the specific winning opening, and the player's confidence in the Pachinko machine can be increased.

[Brief explanation of the drawing]

FIG. 1 is a schematic front view showing one embodiment of the present invention, and FIG. 2 is a schematic perspective view showing one embodiment of the present invention. Figure 3 is a control diagram used in the present invention, Figures 4 and 5 are signal waveform diagrams of clock signals output from the 8-bit binary counter circuit, respectively, and Figure 6 shows the solenoid opening and closing once. Figure 7 is a series of signal waveforms when the solenoid is made to open and close twice. Figure 8 is a series of signal waveforms when the solenoid is made to open and close 18 times. Figure 9 is a series of signal waveform diagrams when the 18th operation winning ball switch is closed while the solenoid is opening and closing 18 times. ■...Winning device lc, ld...Movable piece (guide blade) 2a, 2b-
--Electric drive unit (solenoid) 4... Continuous winning opening 9.11, 12. 15... Drive circuit (flip-flop circuit, Schmitt circuit, delay circuit, reset release control circuit. Reset timing circuit) 10... Operation circuit (8-bit binary counter circuit) Figure 1

Claims (1)

[Claims] (1) A specific winning hole and a winning device are arranged on the game board from which pachinko balls are shot, and the winning device has a continuous winning hole and a movable piece that can be opened and closed with respect to the winning device, and the movable piece is driven to open and close. A pachinko machine is provided with an electric drive unit which generates a drive signal for the electric drive unit based on a winning in the specific winning opening or the continuous winning opening, and a drive circuit that generates a drive signal for the electric driving unit based on a winning in the specific winning opening or the continuous winning opening. A pachinko machine comprising an operation circuit for controlling a drive circuit that generates a drive signal when a wait time has elapsed.