JPH02220459A - Manufacture of gate array - Google Patents

Abstract

PURPOSE:To shorten a development period of a gate array by a method wherein CAD pattern data is divided into first CAD pattern data which surely exists even when types are different and second CAD pattern data which is inherent to the type, and a pattern of the first CAD pattern data is processed in advance. CONSTITUTION:When an Al wiring part on a second layer is formed, CAD pattern data 1a which is inherent to a gate array is transformed in advance into CAD pattern data 1b whose negative and positive have been reversed. When CAD pattern data 2 which is different according to its type is substracted from the pattern data 1b, CAD pattern data 3 whose negative and positive have been reversed is formed. The pattern data 3 is transformed into data for electron-beam exposure use; the Al wiring part on the second layer is formed by using an electron-beam aligner. Accordingly, it is not required to handle the CAD pattern data 1a which is inherent to the gate array whenever the type is different; an amount of data to be handled is reduced. Thereby, a treatment time of the pattern data and a development period of the gate array are shortened.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method for manufacturing a gate array, which improves the method for processing CAD pattern data for semiconductor integrated circuits.

In the conventional gate array, a desired integrated circuit is formed on a semiconductor substrate by arranging gates in rows on a chip and wiring them. As a method for manufacturing a gate array, a method is used in which gates are formed in advance on a semiconductor substrate as mask slices, and only the wiring is changed to form a specific type of integrated circuit.

In recent years, in order to shorten the development period for gate arrays, a method has been adopted in which only the second layer wiring is changed to form an integrated circuit. The method for forming this wiring pattern is as follows: 1. There is no need to manufacture a mask, and the cost of the mask can be reduced.

2. The period required from pattern design to integrated circuit fabrication can be shortened.

3. Patterns can be easily changed.

For these reasons, electron beam exposure equipment is often used. FIGS. 2(a) and 2(b) are a plan view showing the wiring part of a gate array that forms an integrated circuit by changing only the conventional second-layer wiring, and A-A' in FIG. 2(a), respectively. FIG. An example of a connection between logic circuit sections 12 and 13 in which gates are arranged in an array is shown. Interlayer insulating film 5 and fixed first AL wiring 10 on semiconductor substrate 6
, the second AL wiring 11 and the contact portion 4 are formed which change depending on the type of product. The wiring in the X direction is the first AL wiring on the first layer via the pad portion 7! This is done by connecting O and the second AL wiring 11 on the second layer. The pad portion 7 is connected to the first A via the contact portion 4.
Connected to L wiring IO. On the other hand, the wiring in the y direction is formed by intersecting the second ALma line 11 over the first AL wiring 10. The pad portion 7 is CAD pattern data specific to the gate array that always exists even if the product type changes, and there is always a redundant pad portion 7 that is not used for wiring of each type.

Problems to be Solved by the Invention However, according to the conventional configuration, when attempting to process CAD pattern data of a gate array, the CAD pattern data is combined into one. Unique CAD pattern data also needs to be processed at the same time, resulting in an enormous amount of data and a long processing time, resulting in the problem that the development period of the gate array cannot be shortened.

SUMMARY OF THE INVENTION An object of the present invention is to provide a gate array manufacturing method that can shorten the processing time of CAD pattern data and the development period of the gate array.

Means for Solving the Problems The present invention separates CAD pattern data of a gate array into first CAD pattern data that always exists even if the product type is different, and second CAD pattern data that is unique to the product type. It consists of a configuration in which CAD pattern data of 1 is subjected to graphical processing in advance.

Effects of the present invention With the above-described configuration, the first CAD pattern data that always exists even if the product type is different can be processed in advance, reducing the amount of data to be handled and reducing the time required for pattern data processing and the gate array. This makes it possible to shorten the development period.

Embodiment (Embodiment 1) FIGS. 1(a) to 1(c) are plan views showing a method of processing CAD pattern data of a gate array in a first embodiment of the present invention. Hereinafter, a method of processing CAD pattern data of a gate array in which an integrated circuit is formed by changing only the second-layer wiring will be described in accordance with an embodiment of the present invention with reference to FIG.

When forming, for example, AL wiring on the second layer using a positive resist, it is necessary to invert the yin and yang of the CAD pattern data of the gate array. FIG. 1(a) shows CAD pattern data 1a specific to the gate array and CAD pattern data 2 that differs depending on the product type. CAD pattern 1 in advance
a is converted into CAD pattern data 1b specific to the gate array, which is reversed (FIG. 1(b)). Figure 1 (C
), it is possible to form CAD pattern data 3 in which the original yin and yang are reversed. Such pattern data 3 may be converted into data for electron beam exposure, and the AL wiring on the second layer may be formed using an electron beam exposure machine.

In this way, it is not necessary to handle the CAD pattern data 1a specific to the gate array for each type of gate array, and the amount of data to be handled can be reduced.

Further, the processing time of CAD pattern data of the integrated circuit to be manufactured can be shortened, and the manufacturing period of the gate array can be shortened.

In this embodiment, a case in which Yin and Yang are inverted has been described as an example of CAD pattern data processing, but pattern enlargement, reduction, outline processing, etc. can also be processed separately using separate CAD pattern data.

(Embodiment 2) In a second embodiment, a case will be described in which pattern data for a gate array forming an integrated circuit is drawn by changing only the second layer wiring using an electron beam exposure machine.

The CAD pattern data unique to the gate array is processed in advance and converted into data for electron beam exposure. Next, only the pattern data that differs depending on the product type is processed for each product type, converted into data for electron beam exposure, and combined with data for electron beam exposure specific to the gate array. The pattern of the AL wiring on the second M may be formed using the data for electron beam exposure produced in this way. In this way, even if the product type is different, the CAD pattern data specific to the gate array will be
Because it has been converted into data for electron beam exposure in advance,
Data for electron beam exposure only needs to be prepared for parts that differ depending on the product type. Therefore, the amount of data to be handled is reduced, and the time required to prepare data for electron beam exposure can be shortened.

Furthermore, the development period for the gate array can be shortened.

(Example 3) In the third example, similar to the second example, a case will be described in which pattern data of a gate array that forms an integrated circuit is drawn by changing only the second layer wiring using an electron beam exposure machine. do.

Data for electron beam exposure of CAD pattern data specific to the gate array is prepared in advance and drawn on a mask slice. Next, data for electron beam exposure of CAD pattern data that differs depending on the product type is prepared and drawn on a mask slice.

In this way, the amount of data to be handled is reduced and the data processing time is shortened. Furthermore, pattern data specific to the gate array is drawn during the data processing for electron beam exposure, which has pattern data that differs depending on the product.Next, after the data for electron beam exposure, which has pattern data that differs depending on the product, is completed, pattern data that differs depending on the product is drawn. If you draw,
The time from processing pattern data that varies depending on the product to forming the original gate array pattern on a mask slice can be shortened, and the development period of the gate array can be shortened.

In addition, 1. Second. In the third embodiment, a case has been described in which an integrated circuit is formed by changing only the wiring in the second layer, but it goes without saying that the present invention can also be applied to each upper layer other than the second layer. Further, although the wiring pattern is formed using an electron beam exposure machine, it is also possible to use an FIB or to prepare an exposure mask and use an exposure machine such as a stepper.

Effects of the Invention As is clear from the above explanation, according to the pattern data processing method according to the present invention, the CAD pattern data of the gate array is processed into the first C which always exists regardless of the product type.
The amount of data handled by gate array pattern data is reduced by a very simple method of separating AD pattern data and second CAD pattern data specific to the product type, and subjecting the first CAD pattern data to graphical processing in advance. In addition, the processing time for pattern data can be shortened. Furthermore, the development period of the gate array can be shortened.

[Brief explanation of the drawing]

FIGS. 1(a) to (c) are plan views showing a method of processing CAD pattern data of a gate array in the first embodiment of the present invention, and FIGS. 2(a) and (b) are plan views of a conventional gate array, respectively. A plan view showing the wiring part and A- in FIG.
It is a sectional view at A'. 1a...CAD pattern data specific to the gate array, 2...CAD pattern data that differs depending on the product type.

Claims (3)

[Claims] (1) In the graphic processing method of CAD pattern data when a large number of gates are placed on a semiconductor substrate in advance and the gates are later connected to form various semiconductor integrated circuits, the CAD pattern data is A method for manufacturing a gate array, characterized in that the first CAD pattern data is separated into first CAD pattern data, which always exists, and second CAD pattern data, which is unique to the product type, and the first CAD pattern data is subjected to graphical processing in advance. . (2) When drawing the first and second CAD pattern data with an exposure machine, the first CAD pattern data is converted into data for electron beam exposure in advance, and then the second pattern data is 2. The method of manufacturing a gate array according to claim 1, wherein the data is converted into data for beam exposure and then synthesized and exposed. (3) When drawing the first and second CAD pattern data with an exposure machine, draw the first CAD pattern data in advance, and then draw and combine the second CAD pattern data. A method for manufacturing a gate array according to claim 1, characterized in that: