JPH02227743A - Logical simulator - Google Patents

Abstract

PURPOSE:To perform a logical simulation at a function level via a hardware action by carrying out a logical simulation at a function level in response to the description stored in a memory means and storing the executing result of the simulation in the memory means. CONSTITUTION:A control circuit 80 controls each part based on the description of a simulation model stored in a memory FMEM 10 and synchronously with a clock. Then a 1st register FTREG 20 inputs the output of the FMEM 10. An arithmetic circuit 30 inputs the output of the FTREG 20, a 2nd register SDREG 50, or the FMEM 10 and carries out an arithmetic operation related to an operator. An intermediate register IMREG 40 performs an input, and the SDREG 50 inputs the output of the IMREG 40. A stack memory means STUCK 60 inputs the outputs of the SDREG 50 and the FMEM 10 and stacks them. Thus the logical simulation is carried out at a function level in response to the description stored in the FMEM 10 via a hardware action. The result of the logical simulation is stored in the FMEM 10.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a logic simulator, and particularly to a logic simulator that performs functional level logic simulation using hardware.

[Conventional technology]

Conventionally, a logic simulator that performs functional level logic simulation is, for example, rSasaki T etol.

“ A Mixed Level Simula
tor for Large Illigtta
System Logic Verification
n 17th DA Conf, pp626-63
3 (1980) J, it was realized by software.

[Problem to be solved by the invention]

The above-mentioned conventional functional level logic simulators are implemented using software, so the simulation process involves sequential processing of each functional operator, which takes a long execution time, and has the drawback that the simulation time is especially large for large-scale circuits. There is.

The present invention has been made in view of these circumstances,
The purpose is to provide a logic simulator capable of high-speed processing and capable of performing functional level logic simulation in hardware.

[Means for Solving the Problems] In order to achieve the above object, the logic simulator of the present invention includes a storage means in which the description and execution results of the functional level simulation model are stored, and the output of this storage means is inputted. a first register, a second register, and an arithmetic circuit that receives the outputs of the second register, the first register, and the storage means, respectively, and executes arithmetic operations related to a functional operator; an intermediate register which receives the output of the arithmetic circuit as an input and adds the output to the second register; a stack storage means which receives the outputs of the second register and the storage means; and a simulation stored in the storage means. and control means for controlling each of the above-mentioned parts based on the description of the model.

[Effect]

In the logic simulator of the present invention, the storage means holds a description of a functional-level simulation model, and the control means controls each part based on the description, so that the first register stores the output of the storage means. input. The arithmetic circuit inputs the output of the first register, the second register, or the storage means and executes the arithmetic operation related to the functional operator. An intermediate register inputs the output of the arithmetic circuit. The second register inputs the output of the intermediate register, and the stack storage means inputs the output of the second register or storage means and stacks them. A logic simulation of the corresponding functional level is performed, and the execution results are stored in the storage means.

(Example) Next, an example of the present invention will be described in detail with reference to the drawings.

Referring to FIG. 1, one embodiment of the logic simulator of the present invention is a functional level simulation model composed of functional operators, initial values for simulation (initial values of registers, memory, etc., input cover turns, etc.), etc. Memory where descriptions and simulation results are stored (hereinafter referred to as FME)
A first register (hereinafter referred to as FTR) which receives the outputs of a second register (hereinafter referred to as 5DREG) 50 and a stack storage means (hereinafter referred to as 5TUCK) 60;
EG) 20, an arithmetic circuit 30 that receives the outputs of FMEMIO, FTREG 20, and 5DREG 50 and executes shift processing, mask processing, and arithmetic processing related to functional operators; and an intermediate register (referred to as EG) 20 that receives the output of the arithmetic circuit 30 as an input. (hereinafter referred to as IMREG) 40, and rMREG
5DREG50 which inputs the output of 40, and 5TUC where input variables and intermediate states of simulation are stacked.
K60, a stack pointer (hereinafter referred to as 5TPR) 70 that points to the address of 5TUCK60, and FMEMI
It is composed of a control circuit 80 that controls each part based on the description of the simulation model stored in O and in synchronization with a clock. In addition, the symbols 100 to 8 in the figure
00 is a signal line connecting each part.

Referring to FIG. 2, an example of the arithmetic circuit 30 is a high-speed arithmetic unit (hereinafter referred to as FOP) that executes multiple operations using simple logic elements (AND, OR, etc.) at high speed in terms of data flow.
(referred to as an arithmetic unit) 31, and an arithmetic unit (hereinafter referred to as a 10P arithmetic unit) 32 that executes an operation performed by a multiple-input, single-output logic element (such as a large-power single-output AND), and an ordinary two different types of arithmetic unit. An arithmetic unit (hereinafter referred to as 20P arithmetic unit) 33 that performs calculations on inputs, and a shift circuit (hereinafter referred to as SFT) that shifts left and right to extract the data portion necessary for calculation from multiple inputs.
circuit) 34, and a mask circuit (hereinafter referred to as M
(referred to as the SK circuit) 35. F in Figure 1
The output of TREG20 is connected to the input of the 20P arithmetic unit 33 and the SFT circuit 34 via the signal line 300, and the 5DRF
,C.

The output of 50 is sent to the FOP calculator 31 and I via a signal line 600.
It is connected to the inputs of the OP arithmetic unit 32 and the 20P arithmetic unit 33, and the output of FMEM10 is connected to the IOP by the signal line 100.
Arithmetic units 32 and 20P arithmetic unit 33 are connected to the control inputs of SFT circuit 34 and MSK circuit 35 and the input of SFT circuit 34.

Next, the operation of the logic simulator of this embodiment configured as described above will be explained using several examples.

■ to ■ in Figure 3 I) are in the simulation model, D=A*B+C...(1) However, * is logical AND, + is logical OR. The contents of the code stored in FMEMIO are explained in advance. The logic simulation related to the function (1) above is performed as shown in the time chart of FIG. 4 by the control circuit 80 reading the corresponding codes from FMEMIO in the order of numbers ■ to ■ and controlling each part. . Below, the clock (CLK) in Figure 4
The operation will be explained separately for each cycle.

1) Clock cycle-1 First, variable A is read from FMEMI O, and FTR
It is stored in EG20.

2) Clock cycle-2 This variable A is passed through a suitable place in the arithmetic circuit 30 to the IMRE.
Stored in C40. At this time, if the variable A has multiple bits and you want to execute only a specific bit among them, the SFT circuit 34 in the arithmetic circuit 30 shifts the logical operation to the left or right. After bit alignment is performed, the data is stored in the IMREC 40.

At the same time, variable B is read into FTREG20 from FMEMIO.

3) Clock cycle-3 Next, variable B of FTPEG 20 is sent to IMREC 40 via arithmetic circuit 30, and variable A of IMREC 40 is sent to 5DRE.
Each is transferred to G50.

4) Clock cycle-4 Next, variable A of 5DREG50 is FTREG20 and 5
Transferred to TUCK60, IMRE to 5DREG50
Variable B is transferred from C40.

In this state, FTREG20 has variable A, 5DREG5
The variable B is stored in 0 in the form of a combination of bits, and the arithmetic operation of A*B is performed in, for example, the 20P arithmetic unit 33 of the arithmetic circuit 30.

5) Clock cycle-5 The result of A*B is sent to IMREC40. 5D at the same time
Variable B of RBG50 is transferred to 5TUCK60 and FT
The next variable C is taken into REG20 from FMEMIO. At this time, the value of 5TPR70 is increased.

6) Clock cycle = 6 Next, data C of FTREG20 goes to IMREC;40,
The A*B result of IMREC40 is transferred to 5DREG50.

7) Clock cycle-7 Next, variable C of IMREC40 is transferred to 5DREG50, 5D
The A*B result of REG50 is transferred to FTREG20. At the same time, the result of A*B is also transferred to 5TUCK60 with the value of 5TPR70 reduced. At this time, the arithmetic circuit 30
Then, the calculation AjB+C is performed.

8) Clock cycle = 8 Next, the calculation result of A*B+C is sent to IMREC40, 5D
The variable C of REG50 increases the value of 5TPR70 to 5T.
Each is transferred to UCK60.

9) Clock cycle = 9 Next, the calculation result of A*B+C of IMREC40 is 5DRE
Transferred to G50.

10) Clock cycle -10 SDREC; 50 A*B+C operation result is 5TPR7
The value of 0 is decremented and transferred to 5TUCK60, and at the same time, transferred to FMEMIO, thereby ending the logic simulation according to equation (1).

■~[Phases] in Figure 3 ii) are calculated in advance when performing a logical simulation of the function related to the equation H=A*B+C*D+E*F+G...(2) in the simulation model. The contents of the code stored in FMEMIO are explained. The logic simulation related to the function (2) above is performed when the control circuit 80 receives the number ■ from FMEMIO.
This is carried out in the same manner as (1) 2 above by reading the corresponding codes in the order from 0 to 0 and controlling each section.

FIG. 5 i) shows that when performing a logic simulation of the above-mentioned arithmetic expression (2) shown in FIG.
We will explain the contents of the code stored in
i) shows an example of the calculation performed by the FOP calculation unit 31 at that time. In this case, the control circuit 80
Corresponding codes are read from O in the order of numbers ■ to ■ to control each part. By this, first variables A, B
.

C, D, E, F, and G are taken out from FMEMIO and sent to 5D via the arithmetic circuit 30 and IMREG 40.
REG50, and the FO in the arithmetic circuit 30 in FIG.
A*B, C*D, and E*F are computed simultaneously in the P computing unit 31. Note that the variable G is left as is. The result is 5DREG5 via IMREG40.
0, then A*B0C*D+E*F0G is transferred to F
This is performed by the OP calculator 31. And the result is FME
The data is transferred to MIO and the simulation ends.

Comparing the number of instructions in the case of FIG. 5 with FIG. 3 ii), it is 14 in FIG. 3 ii), whereas it is 4 in FIG. 5, which is about 1/3.6. By using the FOP calculator 31 in this way, it becomes possible to perform logic simulations at higher speed. Note that when using the FOP calculator 31, it is necessary to extract and optimize usable conditions at the time of model creation. Normally, control system logic involves many 1-bit operations, so it is effective to apply it to these operations.

〔Effect of the invention〕

As explained above, according to the logic simulator of the present invention, functional level logic simulation can be realized by hardware operation, so this type of logic simulation can be executed at high speed, especially for large-scale circuits. It is very effective to apply the present invention to functional level simulation.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the main part of an embodiment of the present invention, FIG. 2 is a block diagram showing an example of the configuration of the arithmetic circuit 30, and FIG. 3 is a block diagram showing an example of the configuration of the arithmetic circuit 30. 4 is the time chart of FIG. 1 when the logical simulation of the arithmetic expression shown in FIG. 3 i) is performed, and FIG. We will explain the contents of the code that is stored in advance in FMEMIO when performing the logical simulation of the arithmetic expression shown in Figure ii) using another method, and also
3 is a diagram illustrating an example of execution of calculations performed by the P calculation unit 31. FIG. In the figure, 10... Storage means (FMEM) 20... First register (FTREG) 30... Arithmetic circuit 40... Intermediate register (IMREG) 50... Second
Register (SDREG) 60...Stack storage means (STUCK) 70...Stack pointer (STPR)
)80...control circuit

Claims (1)

[Scope of Claims] A storage means in which descriptions and execution results related to a functional level simulation model are stored, a first register receiving the output of the storage means, a second register, and the second register. an arithmetic circuit that takes the outputs of the register, the first register, and the storage means as inputs and executes calculations related to the functional operator; and an arithmetic circuit that takes the outputs of the arithmetic circuit as inputs and adds the output to the second register. an intermediate register; a stack storage means receiving the outputs of the second register and the storage means as inputs; and a control means controlling the respective parts based on a description of the simulation model stored in the storage means. A logic simulator characterized by: