JPH02309428A - Logical simulator - Google Patents

Abstract

PURPOSE:To improve the execution speed by attaining the logical simulation of a function level with hardware. CONSTITUTION:Input setting data for logical simulation and simulated result are stored in a memory 10 and a microprogram execution routine is stored in a memory 20. A memory 30 is old state data storing memory such as a memory element and a register element and a memory 40 stores a simulated model described by function operators as a coded instruction. An arithmetic circuit 50 executes the function operators and a control circuit 60 controls the whole. Thus, the logical simulation of the function level can be attained by the hardware. Thus, the execution speed of simulation can be increased.

Description

TECHNICAL FIELD The present invention relates to a logic simulator, and more particularly to a logic simulator that performs functional level logic simulation.

PRIOR ART Conventional logic simulators of this type are realized by software, and examples thereof include 5asak, I, et al.
-“A Mlxed Level Simulat
or ['or Large Digital Syst
eIIILogic Verif'ic”ation,
”17TIr, DA Conr, ppf126-633
(19110).

Since the conventional functional level logic simulators mentioned above are implemented using software, the simulation process involves sequential processing of each functional operator, which takes a long time to execute, and especially when simulating large-scale circuits, it takes an enormous amount of time. There is a drawback that it becomes .

OBJECTS OF THE INVENTION An object of the present invention is to provide a logic simulator that can implement functional level logic simulation in hardware and significantly improve execution speed.

Configuration of the Invention The logic simulator according to the present invention includes a first storage means in which input setting data for logic simulation and simulation results are stored, and a simulated model described by functional operators in the form of an instruction code. A second storage means, an execution means for executing the functional operator, a third storage means for saving old state data such as memory and registers, and a microprogram for controlling each of these means. a fourth storage means for storing;
The microprogram in the fourth storage means is read in accordance with the instruction code in the second storage means, and the setting data in the first storage means and the saved data in the third storage means are referred to. The method is characterized in that it includes a control means for controlling execution of the execution means.

Embodiments Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention.

In the figure, 10 is a memory (CM) in which input setting data (patterns) for logic simulation and simulation results are stored, 20 is a memory (CS) in which a microprogramming execution routine is stored, and 30 is a memory element or register element. 40 is a memory (DM) for storing old state data, 40 is a memory (IM) in which a simulated model described with a function operator is stored in the form of an instruction code, and 50 is an operation for executing the function operator. The circuit 60 is a control circuit that controls all of these.

100 is a data bus to each memory and circuit, 200 is an address bus, and 300 is a control signal line.

FIG. 2 shows an example of the configuration of the arithmetic circuit shown in FIG. 1. 5
01 is the intermediate register (IMREG), 502 is the second
Register (SD1?BG), 503 is a pointer for honeydware stack (STPR), 504 is a stack (
5TACK), 505 is the second register (PII?EP) connected to the data bus, and 506 is a simple element (AND
, OR, etc.) is a circuit (FOP) that executes multiple operations at high speed in terms of data flow.
A circuit that calculates one output (large-power single-output AND, etc.)
10P), 508 is a normal arithmetic circuit with two different inputs (20P), and 509 is a circuit that shifts left and right in order to extract the data part necessary for calculation from multiple inputs (5F).
T), 510 is a mask circuit (MSK>).

Next, the operation of the embodiment of the present invention will be explained.

First, the functional description I...D-A*B+C in FIG. 3 will be explained as an example. In the above calculation formula, "*" is a logical AN
D. “Ten” represents logical OR. Operations on this expression are performed in the order of numbers ``■'' to ``■'' as indicated by the corresponding instruction codes. This is coded in advance in this order and stored in 1M40, as shown in the correspondence of data in the simulator in FIG.

Next, the simulation operation will be explained with reference to the correspondence of data in the simulation shown in FIG.

It is assumed that necessary data is stored in each memory in the simulator before simulation execution begins. In this example, CMlo has the 1M starting address of description I,
The values of A, B, and C are stored in the IM 40 as described above, and the CS 20 stores the execution start, GET, AND, OR, and EXIT execution routines necessary for the simulation.

The simulation execution order is as follows.

1) When an execution command comes to the control circuit, the execution-start routine of C8 is activated to retrieve the start address of description I from CM. 2) Next, read IM based on this start address and read out the instruction code GET A. (The dotted line from C820 in FIG. 3 indicates control. The same applies hereafter.) 3) Next, read the GET execution routine of C8 that executes this instruction code.

4) By operating this GET execution routine, C
The value of A is read from M to 5TACK 504 of the arithmetic circuit.

5) The LM address is moved to the next address by the control circuit 60, and through the same procedures as (2) to (4), the C
The values from M to B are stored in the 5TACK 504 in the arithmetic circuit 50. (See Figure 3 5TACK (1')) 6) IM
Since the next instruction is an AND, the arithmetic circuit executes A*B from C8 under the control of the AND execution routine, and the result is sent to 5TACK 504.

7) The next command after IM is GET C, so from (2) (
5TACK the value of C from CM using the same procedure as in 4).
Moving on to 04. (See Figure 3, 5TACK (2)) 8) IM
(7) The next instruction is an OR note, C3. (7) Based on the control of the OR execution routine, A*B10 is executed in the arithmetic circuit, and the process goes to 5TACK.

9) The next command of IM is EXIT, which outputs (stores) the result.
Since it is an instruction, the execution result A*B+C is stored in the output value area of CM.

The process of executing A*B+C in the arithmetic circuit is shown in FIG. 5 in the form of a time chart. This completes the series of operations for function description I, and it is ready to wait for the next description to be executed.

Next, an example of using a memory DM that preserves the old state will be described. FIG. 6 shows an example of a memory read function description and the corresponding instruction code, and FIG. 7 shows the correspondence of data in the simulator at that time.

Function description ■ checks the value of RE, and if RE-“1”, ADH
This is an instruction to read 1 word and 16 bits from the address indicated by . Memory M has 1024 words x 16 bits, and the read value becomes the output of memory M.

The start address (Adr) of the functional description H and the start address in the DM of the memory M are set in advance in the CM.

Execution is performed as follows.

1) The value of RE is read from CM and set in the register of control circuit 60.

2) Next, TRN1 is read and the value of RE is checked to check whether to jump to the next address of IM or end. If RE is “1”, get the next instruction within 1M A
DR, otherwise jump to output EXIT.

3) When RE is set to "1" in the above, the GET routine is executed and the value of ADH of CM is set in the register in the control circuit 60.

4) Next, the RAT command is read, and the contents of the word at the ADR-th location (the shaded area in FIG. 3) from the address indicated by the start address of the memory are read and set in the register in the control circuit 60'.

5) Next, the IM EXIT command is executed and the control circuit 6
The memory value of the corresponding ADR in the register 0 is transferred to the CM. When RE is not "1", the state before execution is returned as is.

This completes the series of procedures for function description H.

DETAILED DESCRIPTION OF THE INVENTION According to the present invention, as described in detail, the present invention includes a storage means for storing input setting data and execution results, a storage means for storing a simulation model, a function execution means, a microroutine storage means, By combining this method with a storage means for storing data in the old state, functional level logic simulation can be realized in hardware, and the simulation execution speed can be increased.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a block diagram showing an example of an arithmetic circuit, FIG. 3 is a diagram showing an example of a functional description and the corresponding instruction code, and FIG. Figure 5 is a time chart showing the execution process of the function description in Figure 3. Figure 6 is another example of the function description and its correspondence. FIG. 7 is a diagram showing the correspondence of data in the simulator when the functional description of FIG. 6 is executed. Explanation of symbols of main parts 10... Memory for input data setting 20...
...Memory for microroutine 30 ...Memory for data storage 40 ...Memory for simulated model instruction code

Claims (1)

[Claims] (1) a first storage means in which input setting data for logic simulation and simulation results are stored; a second storage means in which a simulated model described by functional operators is stored in the form of an instruction code; Execution means for executing the functional operator; third storage means for storing old state data such as memory and registers; and fourth storage for storing microprograms for controlling each of these means. reading the microprogram in the fourth storage means according to the instruction code in the second storage means and referring to the setting data in the first storage means and the saved data in the third storage means. and control means for controlling the execution of the execution means.