JPH0223659A - Semiconductor integrated circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION (A) Field of Industrial Application The present invention relates to semiconductor integrated circuits, and in particular to a pattern layout that can be easily expanded to meet the demands of custom ICs.

(b) Conventional technology in general is disclosed in Japanese Patent Application Laid-Open No. 59-84542 (HOI L
21/76), a semiconductor integrated circuit technology in which a plurality of circuit blocks are formed on the same semiconductor substrate has the configuration shown in FIG.

FIG. 8 is a schematic plan view of the semiconductor chip (101), and a to f indicate circuit blocks. These circuit blocks handle different frequencies and signal levels, and
The functions are also different.

This circuit block is formed in an N-type region (103) on a P- type semiconductor substrate (102) as shown in FIG. 9, and each circuit block is formed in a highly doped P+-type region ( 104). Here, block b and block C are shown.

The P1 type area (104) for this partition has one end connected to P1.
The other end is connected to the ground line (102) through the oxide film (105) on the semiconductor surface.
106).

A ground line (106) extends from each block to the ground bonding pad GND located at the left end of the integrated circuit.

Next, as shown in FIG. 8, the power lines (Vcc) of each block circuit are gathered around the outer periphery of the integrated circuit and individually connected to power supply bonding pads. On the other hand, since the circuit blocks a to f have different functions, the number of elements present in each block is different, and the block sizes are different.

(c) Problems to be Solved by the Invention As mentioned above, since the circuit blocks a to r have different sizes, all of these circuit blocks can be efficiently integrated into a semiconductor chip (
101>, the sizes of each circuit block interact with each other, making it difficult to integrate them into the same chip.

Also, if you delete circuit block a and insert another circuit block a' with improved characteristics, or if you try to add circuit block g with a different function to the circuit block configuration shown in Figure 8, each program -Since the size of the Tsuku was different, it was necessary to recreate all the patterns.

On the other hand, the MOS type capacitor included in the circuit block has a very large area, making it difficult to arrange it in the circuit block.

Therefore, in recent years, the lifespan of products has become extremely short, and when a user tries to incorporate a unique circuit desired by a chip into a certain chip, even though the user wants a short delivery time, the circuit The problem was that it required a very long lead time to remake the pattern.

Furthermore, since a MOS type capacitor is generally formed in an N type island region surrounded by a P+ type heel region or an N+ type buried region, a PN junction capacitance is generated.

The PN junction capacitance B occurs at the junction between the N-type island region and the P"-type divided region, or at the junction between the N-type island region or the N+ type buried region and the P-type semiconductor substrate.

On the other hand, since this MOS type capacitor has a very large area, the PN junction area naturally increases, and the capacitance value becomes very large. Therefore, there has been a problem in that leakage current from this capacitor flows into the semiconductor substrate, adversely affecting other electronic circuit blocks.

(d) Means for solving the problem The present invention has been made in view of the problem, and solves the problem by
The top surface of the semiconductor chip (1) is divided into a large number of mats of substantially the same size, and a plurality of electronic circuit blocks with different functions are accommodated in one or more integral number of mats, and the electronic circuit blocks include This problem can be solved by integrating the capacitors (7) that are connected to each other on a specific mat.

Further, electrodes (26>, (27), (28) are provided in contact with the separation region (18) around the specific mat where the capacitor (7) is integrated or in the region of the mat,
This problem is solved by sucking out the leakage current with this electrode.

(E) Function According to the present invention, the semiconductor chip (1
) dividing the top surface into a number of mats of substantially the same size;
A plurality of electronic circuit blocks having different functions are housed in an integral number of mats, and a capacitor (7) included in the electronic circuit block is integrated in a specific mat within the integral number of mats, and the capacitor (7) Since the capacitors are connected to the desired circuit in multiple layers, the layout of the capacitor is very easy, and it is also possible to design each electronic circuit block and divide the electronic circuit block into a fixed number of elements to design each component. Become. Therefore, parallel design can be performed by dividing each electronic circuit block, and the design period can be significantly shortened. Furthermore, since circuit changes can be made for each electronic circuit program and for each mat, there is no need to change the design of the entire IC.

On the other hand, around a specific mat where capacitors can be integrated, as shown in FIGS. 2A to 2C, a P+ type isolation region (
18) and the ground line (27) in contact with P
A ground line (26) in contact with the + type isolation region (18) and a suction electrode (28) arranged in a comb-teeth shape are formed to drain the leakage current generated from the lower layer of the MOS type capacitor (7). Electrode (26).

(27), (28>).Also, since the capacitor is integrated in a specific mat, leakage current can be concentrated around this specific mat.Therefore, it affects other electronic circuit blocks. It is possible to eliminate leakage current that causes

(F) Embodiment First, a first embodiment of the present invention will be described in detail with reference to FIG.

The upper surface of the semiconductor chip (1) is divided into 10 mats A to J. There is a power line (2
) and Guérande lines 3) are extended in parallel and adjacent to each other (already divided).

The arrangement of the power supply line (2) and ground line (3) forming the division line (4) is such that the power supply line (2) shown as a solid line is provided on the left side of each mat A-J, and the ground line (shown as a dashed line) is provided on the right side. 3) is provided.

Therefore, only the division lines of mat A and mat J at both ends are formed of either the power supply line (2) or the ground line (3), and the intermediate division line is formed of both. A power line (2) and a ground line (3) adjacent to each mat A-J are integrated in each mat and supply power to the circuit blocks.

In addition, the power supply line (2) and ground line (3) of each division line (4) are connected to the first line formed above and below the mat.
are connected to a supply line (5) and a second supply line (6) in a comb-teeth shape, respectively, and the first and second supply lines (5) and <6) are provided around the pellets. ■Power supply pad among the pads. . and is led to the ground pad GND.

As will become clear, each power line (2), ground line (3), and first and second supply lines (5)
, (6) is basically realized by one wiring in one layer of two-layer wiring.

Each mat A-J divided by the above-mentioned division line (4)
are formed into a shape of substantially the same size, specifically, the width is set so that six NPN transistors are lined up, and the length is set to a certain number of elements that is easy to design, for example, about 1
The settings are such that 00 elements can be laid out. The size of this mat can be arbitrarily selected depending on the number of elements that can be easily designed depending on the electronic circuit block to be integrated.

The circuit elements integrated within the mat are composed of transistors, diodes, resistors, and capacitors, and are separated by normal PN isolation, and the connections of each element are connected by the first electrode layer of the two-layer wiring. Generally, there is crossover at the second layer of electrodes. Also, as will become clear later, the main capacitors (7) included in the electronic circuit blocks of Mat E to Mat J are represented by the rectangles with broken lines on Mat E.
are concentrated in

Next, with reference to FIGS. 3A and 3B, the circuit elements integrated within the mat and the partition lines (4) will be specifically described.

FIG. 3A is an enlarged top view of the vicinity of mat B.

The division line (8) shown by the dashed-dotted line on the left is the division line (4) provided between mat A and mat B in Fig. 1, and the division line (9) shown by the dashed-dotted line on the right is , 1st
The division line provided between mat B and mat C in the figure (
4). And this division line (8), (9)
In between, there is a transistor (10), a diode (11), a resistor (12) and a capacitor (13) indicated by dotted lines.
are accumulated. Although these elements are shown sparsely in the drawing, they are actually densely integrated. In addition, the wiring between elements within the mat is the first layer of electrode layer (shown by a dashed line).
14), and wiring between mats A and B and between mats B and C, such as signal lines and feedback lines, is formed of the second electrode layer (15) shown by solid lines. These first and second electrode layers (14) and (15) are connected at contact regions indicated by X marks.

FIG. 3B is a sectional view taken along line AA' in FIG. 3A. An N-type epitaxial layer (17) is laminated on a P-type semiconductor substrate (16), and this epitaxial layer (
17) P+ reaching the semiconductor substrate (16) from the surface
A mold isolation region (18) is formed and a number of island regions are formed. Inside this island region (19) are an NPN transistor (10) and a diode (11).
, a resistor (12), a capacitor (13), etc. are made, and the collector region (2) of the NPN transistor (10) is
0) and the semiconductor substrate (16) or between the island and the substrate (19).
1) is formed. The epitaxial layer (17)
For example, a silicon oxide film (22
) is formed, and a first electrode layer (14) is formed on this silicon oxide film (22). Further, an insulating film (23) such as PIX is formed to cover this first electrode layer (14), and a second electrode layer (15) is formed on this insulating film (23). has been done. Further, the power supply line (2) and the ground line (3) are provided on the isolation region (18), and the ground line (3) is in ohmic contact with this isolation region (18) to stabilize the substrate potential. We are trying to change the world.

Next, the relationship between the electronic circuit block incorporated in this configuration and the mat will be described. Here, two electronic circuit blocks shown in FIG. 6 are used, for example, a multiplex decoder block (24) that demodulates a stereo signal, and an FM-IF block (25) that amplifies an intermediate frequency signal and then detects it to obtain an audio signal. will be incorporated.

The number of elements in this multiplex decoder block (24) is approximately 390, and the FM-IF block (25)
There are approximately 430 pieces. Therefore, the former is divided into four parts with 1°O elements or less as a guide, and each part is integrated into mats A to D, and the function between each mat is determined by the second electrode layer (as described above). 15) is provided to realize an electronic circuit block. The latter is also divided into five parts with 100 elements or less as a guide, and each part is integrated into mats from E to E, and the function between each mat is determined by the second electrode layer (15) as described above. is provided to realize an electronic circuit block. Furthermore, the mat J integrates optional circuits provided by the user, such as circuits for further improving the performance of the present IC.

On the other hand, the capacitor (7) incorporated in the FM-IF block (25) is integrated in the mat E.

In FIG. 1, 11 capacitors are formed, which are indicated by broken lines. The leakage current generated from the area of mat E where the capacitor is formed is shown by the ground lines (26) and (27) indicated by dashed lines formed on both sides of mat E.
The air is sucked out using a ground line (26) and a suction electrode (28) arranged in a comb-like shape. A partially enlarged view of this mat E is shown in FIG. 2A.

-The thickest electrode (29), (30) shown by the dotted chain line
are the ground lines (26) and (27) formed on both sides of mat E in FIG. A MOS type capacitor (7) is formed between these two ground lines (29) and (30), and the hatched part corresponds to the upper layer electrode (31) of the capacitor, and the first layer formed into eyes. Further, this upper layer electrode (31) is in ohmic contact with the second layer electrode (33) via the contact (32) indicated by the X mark on the right side, and this electrode (33)
) extends to the right and is connected to the circuit elements included in the electronic circuit block. Further, the upper layer electrode (31)
The contacts (34) indicated by X marks on the top and bottom or left and right sides correspond to the P-type diffusion region (35) formed in the lower layer of this upper layer electrode (31) shown in FIG. 2B and the lower layer electrode of the capacitor. The contact portion with the electrode (36) is shown. Here, the electrode (36) is hereinafter referred to as a lower layer electrode. Like the upper layer electrode (31), this lower layer electrode (36) is in contact with the second layer electrode (38) via a contact (37). This second layer electrode (38) extends to the right and is connected to the circuit elements included in the present electronic circuit block.

Here, the contact (32) of the upper layer electrode (31) is provided near the left side of the ground line (30) to prevent the second layer electrode (33) extending from there in the direction of the mat F from crossing. It is provided in a straight line for this purpose.

Further, since the signal flow in the circuit is from the top to the bottom of the mat F, this capacitor is also substantially provided in the circuits from top to bottom.

Next, a cross-sectional view of this IC will be explained. Cross-sectional views taken along lines AA' and BB' in FIG. 2A are illustrated in FIGS. 2B and 2C.

First, there is a P-type semiconductor substrate (16), and on this semiconductor substrate (16) there is an N-type epitaxial J! (17) are stacked. A P-type isolation region (18) reaching the semiconductor substrate (16) from the surface of this epitaxial layer (17)
Each capacitor (7) is formed in an island surrounded by this isolation region (18). There is an N+ type buried layer (40) in the main region of this island (39), a P+ type diffusion region (41) is formed in the upper layer of this buried layer (40), and this diffusion region (41) and Overlapping P-type diffusion regions (35) are formed. And on this epitaxial layer (17) is an insulating film of SiOx.
There is a film (22), and on this Sin film (22) are an upper layer electrode (31), a lower layer electrode (36), and a ground line (
29), (30) and suction electrode plate 28) are formed. This ground line (29), (30
) and the suction electrode (28) are in contact with each other over substantially the entire surface, as shown in the hatched contact area in FIG. 2A. Then, a second layer of insulating film, for example, PIX (23) is coated, and electrodes (33) and (38) extending to the mat F are formed.

Therefore, a junction capacitor formed around or below this MOS type capacitor (7), such as an island (39
>, the isolation region (18), the island (39), the semiconductor substrate (16), and the buried layer (40).
A ground line (29) through the isolation region (18),
(30) or suction electrode (28).

Next, a second embodiment of the present invention will be described in detail with reference to FIG. In this embodiment, the upper surface of the semiconductor chip (42) is divided into regions (43) indicated by two-dot chain lines, so that the upper surface of the semiconductor chip (42) has substantially the same shape.
It is characterized in that it is divided into two equal parts, the first and second regions (44) and (45), and a large number of mats are provided in each region (44) and (45). As a result, since the number of mats is large, the layout of the semiconductor chip (42) is easier than in the first embodiment.

Specifically, 10 mats of A-J are formed in the first region (44), and 10 mats of N-T are formed in the second region (45).
The structure of each mat is the same as in the first embodiment, with substantially the same space capable of integrating about 100 elements, and each mat is separated by a partition line (4).

However, the capacitor included in this electronic circuit block is integrated in the mat E in order to intensively absorb leakage current to the substrate.

The 20 mats listed above contain AM/FM as shown in Figure 6.
A 1-chip stereo tuner IC is formed. 6th
The figure is a block diagram explaining this electronic block circuit, and includes a 2M front end block (46), an FM-I F
block (25), noise kiln cellar block (47)
), multiplex decoder block (24), A
It is composed of a total of five electronic circuit blocks, including an M tuner block (48). Although each circuit block is well known, its function will be briefly explained.

First, the FM front end block (46) is a channel selection part for FM broadcasting, and receives an FM broadcasting signal of several tens of MHz to several hundred MHz and converts the frequency into an intermediate frequency signal of 10.7MHz. There are about 250 of them, so they are integrated into the -M mat. Next, FM-IF
The block (25) amplifies this intermediate frequency signal and then detects it to obtain an audio signal, and has about 430 elements, so it is integrated in the mats E to E. Next, the noise canceller block (47) removes pulse noise such as ignition noise, and has about 270 elements, so it is integrated into an NP mat. Furthermore, the multiplex decoder block (24) is a block for demodulating stereo signals, and has about 390 elements, so it can be integrated into a QT mat. Finally, the AM tuner block (48) is a channel selection part for AM broadcasting, and converts the AM broadcasting signal received by the antenna to an intermediate frequency (a 50KHz), detects it, and obtains an audio output. Since it has several elements, it is integrated in mats A to D.

Furthermore, in FIG. 7 A1, FIG. 7 B, and FIG. 7 C,
A diagram in which a tuner block (48), a front end block (46), an FM-IF block (25), and a multiplex decoder block (24) are further divided into blocks is shown.

First, the local oscillation circuit (OS C) (49) in the AM tuner block (48) in FIG. 7A is connected to mat A, the mixing circuit (MI G C) (51), high frequency amplification circuit (RF) (52) and intermediate frequency amplification circuit (IF) (5
3) is substantially integrated into the mat C, a detection circuit (DET) 54) is substantially integrated into the mat D, and the power supply pad (2) is connected as shown in FIG. o
The third power supply line (55), (56), (57), which is shown by the three-dot chain line and extends from the l in a cylindrical shape with four lines,
(58) to the first power supply line (59) of the mats A to D. 0 is supplied. Also, the ground bad GND 1 has three octopus-like trees installed between mat M and mat N! 9- Second ground lines (61), (62) indicated by three-dot chain lines on one end divided region (43) via electrode (60)
, (63), and the respective second ground lines (61), (62), (63) are connected to the first ground lines (64) of the A-D mats.

Next, the high frequency amplification circuit (65) and the mixing circuit (65) in Fig. 7B are shown.
6) and a local oscillation circuit (67), the front end block <46) handles extremely small level signals of several μ■, so it
It dislikes interference from the F block (25), and the local oscillation circuit <67) within this block oscillates itself, generating unnecessary radiation. Therefore, the FM-IF block (25) is particularly spaced apart, and since the oSC block hates interference the most, a separate power supply V is provided. C81VCC41GND3, G
ND4 is used.

That is, the FM-IF block (25) is diagonally diagonally integrated with the -M mat, the local oscillation circuit (67) is integrated on the cornermost mat K, and on both sides there are other pads (2). A first power line 8) and a ground line (69) are provided through o4 and GND4. In addition, the mat of M is connected to VCC3 and GND3.
Through these, respective first power and ground lines (70) and (71) are provided.

On the other hand, the FM-IF block (25), which is composed of an intermediate frequency amplification circuit (72), a detection circuit (73), an S meter (74), etc., is integrated on the E-I mat, and the detection circuit (73) is on mat I, S meter (74) etc. is on mat G
Furthermore, the limiter circuit, mute circuit, etc. in the intermediate frequency amplification circuit (72) are substantially integrated on the E, F, and G mats.

Here, as explained in the first embodiment, the capacitor included in the limiter circuit is integrated in the mat E. This mat E is shown in Fig. 2 A, Fig. 2 B, and Fig. 2
Although it is substantially the same as Figure C, the ground lines (75) and (76) formed around the mat E are different. The ground line (75) connects the semiconductor chip (4
2), connects to GND2, contacts the isolation region below, and absorbs the meter current around the mat E capacitor and chip. In addition, the ground line (76) shares GND with a chisel circuit other than the capacitor included in the mat F, and allows leakage current from the mat E in the direction of the mat F to flow through the electrode (60) to GNDI. .

Further, the electrode (77) on the left periphery of the chip (42) also sucks out leakage current.

Here, the limiter circuit with an extremely high gain of 80 to 100 dB, the detection circuit (73) with a large signal level, the limiter circuit and the S meter (74) with a large signal level generate oscillation due to feedback, and the detection circuit (73) and the S meter (74) have a high signal level. Meter (74
), the characteristics deteriorate due to mutual interference, so matte F,
The first power line (78) of G is connected to the third power line (57) shown by the three-dot chain line in the book, and the first power line (79) of mats H and I is connected to the third power line (57) shown by the three-dot chain line in the book. Power line (56)
It is connected to the. Mat J also integrates optional circuits provided by the user, and this power line (8
0) is also connected to the negative third power supply line 55).

Also, the first ground line shown by the dashed line on the E-J mat is a second ground line (61) that extends from the ground pad GNDI in a leg shape and is connected at one end.
, (62), and (63) are connected in the same manner as described above.

Next, the DC amplifier circuit 81) and the decoder circuit (81) of the multiplex decoder block 24) in FIG.
2), the lamp driver circuit (83) is connected to mat Q and mat R, and the phase comparator circuit (84), low-pass filter circuit (85), voltage controlled oscillator (86), frequency dividing circuit (87), etc. are connected to mat S. The three electrodes (88), (89), and (90) that are substantially integrated in the mat T and extend from the power supply pad VCC1 in an octopus-like shape are as follows:
It passes between the AM tuner block (48) and the FM-IF block (25) and is connected at one end to the second power lines (91), (92), (93) on the divided area (43). One tree extends to the mats Q and R, one tree extends to the mats S and T, and one tree extends to the N-P mat that becomes the noise canceller block (47).

On the other hand, the ground pad GND2 has three third
The ground lines of (94), (95), (96
), and as before, the N-P mat, Q, R
mat, S and T mats.

As described above, similarly to the first embodiment, the mats A-J and -T are divided by the division line (4) consisting of the first power supply line and the first ground line. In addition, since the first power supply line and the first ground line are formed in a substantially comb-like shape, the space between the mats and the surrounding space can be effectively utilized.
2) Surrounding bad V. ct, GNDI, GND
2 can be connected in the shortest distance.

Next, countermeasures against interference between the FM front end (46) and the FM-IF block (25) will be described. Conventionally, individual IC
It was a problem with the set board because I was using each of them, but
This time, because of the single-chip configuration, this interference became a problem, but it was solved by the following measures.

First, as mentioned above, the FM front end block (46
) handles extremely small level signals of several μV, so
Because it dislikes interference from other circuit blocks, especially the FM-IF block (25), and because the local oscillation circuit (67) configured within this block oscillates itself and generates unnecessary radiation, it must be separated from other blocks. or provide a separate power source.

For these reasons, first, the FM front end block and the FM-IF block were provided diagonally, and the local oscillation circuits in these blocks were integrated on the mat K and separated from each other. Next, AM tuner block (48) and FM-I
F block (25), FM front end block (
46) and the noise canceller block (47),
In other words, by widening the partition line widths of mat P, mat E1, mat M and mat N, the FM front end block (46) can be separated from other blocks, especially the FM-IF block (
25). Further, between the mat D and the mat E and between the mat M and the mat N, an electrode (88) extending from the power supply pad VCC* to the second region (45),
(89), (90) and an electrode (60) extending from the ground pad GND1 to the first region (44>), and furthermore, a second power line (91) is provided on the divided region (43).
, (92), (93) and second ground lines (61), (62), (63).

Therefore, the FM front end block (46) is connected to the adjacent FM-IF block (25), AM tuner block (48) and noise canceller block (47).
Especially the power line (88), (89)
, (90> prevents unnecessary radiation and connects the ground line (6
0) is in contact with the isolation region, so it can suck out the substrate current and prevent interference.

Also, since the local oscillation circuit (67) in this FM front end block (25) dislikes interference, the power supply bad V
. c4 and a ground pad GND4 are provided separately, and external circuits are supplied by a power supply pad VCCs and a ground pad GND3.

Furthermore, the FM-IF block (25)
This circuit is integrated with mat E and mat F.

The capacitor in this limiter circuit causes leakage to the substrate as described above, and this leakage current flows to the FM front end, causing malfunction. Therefore, the capacitors are grouped together in the mat E, and the first ground line (75) of the division lines (4) on both sides of the mat E.

The first ground line (75) is connected to the FM-IF block (25).
), are extended around the outer periphery of the multiplex decoder block (24) and noise canceller block (47) to also suck out leakage current arising from these.

Also, due to wiring reasons, the third power supply line (55), (5
6), (57), (58), divided area (43)
Upper second power line (91), (92), (
93) and the second ground line (61), (6
2), (63), etc. cross over via the through holes shown by black circles and the second electrode layer shown by dotted lines. In particular, the AM tuner block (48) does not operate simultaneously with other block circuits, so the AM tuner block (48) and FM-IF block 25)
One pad V. They share the ol, so there is a crossover. Also, Grand Rose l-”GND
The same applies to 1.

Figure 5 specifically shows the configuration of the electrodes to explain that the FM front-end block (46) and FM-IF block (25) are separated and crossed over, as described above. . The area indicated by the X mark is the through hole indicated by the black circle. - Finally, let's take a look at an example of the features of the present invention. For example, AM tuner block (48)
If it is not necessary, the four mats forming the multiplex decoder block (24) are directly integrated into the mats A to D, and mats I and J, for example, are integrated into the remaining mats Q and R. Therefore, since the I, J, S, and T mats are redundant, by deleting these mats, the mats can be arranged neatly in a rectangular chip.

Here, the first layer wiring within the mat can be used as is, and only the wiring between mats and the wiring between blocks need be considered.

Also, when partially improving the FM-IF block (25),
For example, it is only necessary to take out the mat F, which is the improved part, and improve it, and the other mats E, G, and H can be used as they are. Also, when adding another block that is an option for the user, all the mats can be used as is and only the required number of mats can be added to this block, and in this case mat J is used as the mat for this option.

In other words, since mats of the same size are formed in a matrix, replacement, addition, and deletion are very easy.

(g) Effects of the invention As is clear from the above explanation, the first effect is the division line (4
), the top surface of the semiconductor chip (1) is divided into a number of mats of substantially the same size, and electronic circuit blocks with different functions are accommodated in an integral number of mats, making it possible to design each electronic circuit block in parallel. , the design period can be significantly shortened. Furthermore, since the electronic circuit block can be divided into a fixed number of elements and designed for each mat, parallel design for each mat can be performed. Further, since circuit changes such as deletion, addition, and modification can be designed for each electronic circuit block or each block, it is sufficient to make changes for each block or each mat, and there is no need to change the design of the entire IC. Furthermore, since mats can be made into cells as basic blocks, once the design is completed, when changing the circuit afterwards, only the mats to be changed need to be modified, and the other mats can be used as is, resulting in extremely high reliability.

Further, by integrating the capacitors included in the electronic circuit block in a specific mat among the mats forming the electronic circuit block, the design becomes easy. This means that by integrating capacitors within a specific mat, transistors, diodes,
and because it is not restricted by the shape of the resistor. Moreover, since the other mats do not contain capacitors, there is no interaction with the capacitors, and the design of these mats becomes easier.

Second, if a mat in which capacitors are integrated is surrounded by a separation region, the leakage current of the junction capacitance flowing out from this mat portion can be sucked out by the separation region around the mat.

Thirdly, by bringing this separation region into substantially entire contact with the ground line, leakage current generated from the capacitor can be sucked out to the outside via the ground line without flowing to other mats.

Fourth, by surrounding the capacitor with a separation area, leakage current can be sucked out for each capacitor, and the surrounding area of the mat can be
Double suction can be achieved by surrounding the capacitor.

Fifth, by providing the ground line and the suction electrode in a comb-teeth shape, an integer number of capacitors can be installed between the comb-teeth, and the leakage current of the capacitor can be sucked out for each integer number of capacitors. be able to. Furthermore, as shown in FIG. 4, by forming a comb-like shape with the left ground line, leakage current to the left can be intensively sucked out, and in particular, it can be prevented from returning to the front end block.

Sixth, since the upper and lower electrodes of a capacitor of a specific mat are, in principle, formed in the first layer, the partition line (
The second layer can be used for wiring with other mats beyond 4), and the wiring for the capacitor and the wiring for other elements can be distinguished, making the design extremely easy.

Seventh, the upper layer electrode (31) and electrode (33) of the capacitor
By arranging the contact (32) with the mat on the right side of the mat, the second layer electrode (33) can be provided in a straight line on the mat on the right, and the second layer of the mat on the right The layout of the electrodes can be made extremely easy.

Eighth, by providing the capacitors from above or below to below or above a specific mat in accordance with the order of the circuits in the electronic circuit block, the second layer electrode (33) extending to the mat on the right ( 3B> pattern layout can be facilitated.

Ninth, by providing a specific mat with integrated capacitors on the mat at one end of the area constituting the electronic circuit block, the connection electrodes (33) and (3B> with other mats can be extended in only one direction. This makes pattern layout easier.

[Brief explanation of the drawing]

FIG. 1 is a top view showing a first embodiment of the semiconductor integrated circuit of the present invention, FIG. 2A is a top view showing a specific mat in which capacitors are integrated in FIG. , Figure 2A
A cross-sectional view taken along line A-A' in Figure 2C is BB-B in Figure 2A.
3A is a top view showing a normal mat, FIG. 3B-32= is a sectional view taken along line A-A' in FIG. 3A, and FIG. 5 is a top view showing the actual electrode pattern of FIG. 4, and FIG. 6 is a block diagram of an electronic circuit incorporated in the semiconductor integrated circuit of the present invention. , FIG. 7A is a diagram explaining the AM tuner block, and FIG. 7B is a diagram explaining the FM front end block and FM-I.
FIG. 7C is a diagram explaining the multiplex decoder block, FIG. 8 is a top view of a conventional semiconductor integrated circuit, and FIG. 9 is a diagram explaining the block B and C in FIG. FIG. (1) , (42>...semiconductor chip, (2)
...Power line, (3)...Ground line, 4)
... compartment line, (5) ... first supply line,
(6)...Second supply line, (7>...Capacitor (43)...Divided area, (44)...First area, (45)...Second area, (55),
(56), (57), (5B)...Third power supply line, (61), (62), (63)...
...Second ground line, (91), (92)
, (93)...second power line, (94)
, (95), (96)...Third ground line. Figure 7△ Figure 7B 81 7th! tic

Claims (9)

[Claims] (1) A semiconductor chip is formed by dividing a semiconductor chip into a plurality of regions of substantially the same size by arranging a plurality of division lines in the same direction, each of which is a set of power supply lines and ground lines extending adjacent to each other. a mat, and an electronic circuit composed of a plurality of electronic circuit blocks having different functions incorporated in an integral number of the mats of the semiconductor chip, and a capacitor included in the electronic circuit block is connected to a specific circuit forming the electronic circuit block. A semiconductor integrated circuit characterized by being integrated into a mat. (2) The semiconductor integrated circuit according to claim 1, wherein the mat in which the capacitors are integrated is surrounded by an isolation region formed within the semiconductor substrate. (3) The semiconductor integrated circuit according to claim 2, wherein the ground line formed around the mat in which the capacitors are integrated and the isolation region are in contact over substantially the entire surface. (4) The semiconductor integrated circuit according to claim 1, wherein the capacitor is surrounded by an isolation region formed within the semiconductor substrate. (5) The semiconductor according to claim 1, wherein the extraction electrode arranged in a comb shape with the ground line is provided between vertically adjacent capacitors, and is in substantially entire surface contact with the isolation region provided between the capacitors. integrated circuit. (6) The semiconductor integrated circuit according to claim 1, wherein the wiring between the capacitor and the element formed on the mat is substantially formed in the second layer. (7) Claim 6, wherein the upper electrode of the first layer constituting the capacitor substantially contacts the wiring of the second layer near one side that contacts the mat on which semiconductor elements other than the capacitor are formed. The semiconductor integrated circuit described. (8) The semiconductor integrated circuit according to claim 1, wherein the capacitors are provided from the upper end or lower end of the mat on which the capacitors are integrated in accordance with the order of the circuits of the electronic circuit block to the lower end or upper end of the mat. (9) The semiconductor integrated circuit according to claim 1, wherein the mat on which the capacitors are integrated is provided at one end of the area constituting the electronic circuit block.