JPH0223663A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To assure a layout systematically substantially without influencing on a pattern arrangement of a block region by providing a plurality of pads for each block region and forming a protective diode using a lower layer region. CONSTITUTION:Pads 90, which are employed for an input/output signal to/from a semiconductor chip 1, are provided around the chip 1 for each electronic circuit block. An N type first diffusion region 92 is provided in a region in a lower substrate of power supply lines 35, 36, 37, 38 where there is formed nothing, an N type second diffusion region 93 is provided in a lower layer of the pad 90, and a p type third diffusion region 94 is provided in the region 92. These regions 92, 93, 94 are a cathode of a diode D1, a cathode of a diode D2, and an anode of the diode D1. Additionally, an anode of the diode D2 serves as a p type semiconductor substrate. The region 92 is provided by one for each block region, so that even if any noise enters the region 92, only this block region is interfered without influence on any other block region. Thus, a layout is systematically assured substantially influencing on a pattern arrangement of the block region.

Description

DETAILED DESCRIPTION OF THE INVENTION (A) Field of Industrial Application The present invention relates to a semiconductor integrated circuit, and particularly to a semiconductor integrated circuit having a pattern and layout that can be easily expanded to meet the demands of custom ICs. The invention further relates to a semiconductor integrated circuit having a surge protection device for preventing dielectric breakdown.

(b) Conventional technology in general is disclosed in Japanese Patent Application Laid-Open No. 59-84542 (HOI L
21/76), a semiconductor integrated circuit technology in which a plurality of circuit blocks are formed on the same semiconductor substrate has the configuration shown in FIG.

FIG. 8 is a schematic plan view of the semiconductor chip (201>, in which a to f indicate circuit blocks. These circuit blocks handle different frequencies and signal levels, respectively.
The functions are also different.

This circuit block is formed in an N-type region (203) on a P- type semiconductor substrate (202) as shown in FIG. 204). Here, block b and block C are shown.

The P+ type area (204) for this partition has one end connected to P
It is in contact with a - type semiconductor substrate (202), and the other end is ohmically connected to a ground line (206) through an oxide film (205) on one semiconductor surface.

A ground line (206) extends from each block to the ground bonding pad GND at the left end, converging in the center of the integrated circuit.

Next, the power lines (V.C) of each block circuit are grouped around the outer periphery of the integrated circuit and individually connected to power supply bonding pads, as shown in FIG.

On the other hand, since the circuit blocks a to f have different functions, the number of elements present in each block is different, and the block sizes are different.

(c) Problems to be Solved by the Invention As mentioned above, since the circuit blocks a to f have different sizes, all of these circuit blocks can be efficiently integrated into semiconductor chips (
201), the sizes of each circuit block interact with each other, making it difficult to integrate them into the same chip.

Also, if you delete circuit block a and insert another circuit block a' with improved characteristics, or if you try to add circuit block g with a different function to the circuit block configuration of FIG. 8, each block Because the sizes were different, it was necessary to recreate all the patterns.

Therefore, in recent years, the lifespan of products has become extremely short, and when a user tries to incorporate a unique circuit desired by a chip into a certain chip, even though the user wants a short delivery time, the circuit The problem was that it required a very long lead time to remake the pattern.

On the other hand, as semiconductor chips become smaller, damage caused by static electricity has become an important issue. This destruction occurs when an electrostatic surge is applied in the opposite direction to the PN junction, charge carriers are accelerated at this junction, causing avalanche collapse. It is thought that this collapse concentrates at the extremes of the junction, leading to destruction of the crystal lattice.

As a measure to prevent this destruction, a measure as shown in FIG. 10 has been considered. However, when attempting to realize this circuit, the layout and connections on the board become complicated, resulting in a complicated design.

(d) Means for Solving the Problems The present invention has been made in view of the above problems, and for each block area in which all electronic circuit blocks are formed, a plurality of pads (90) derived from the electronic circuit blocks are provided. This is solved by providing protection diodes on the sides of the block area (91) corresponding to the periphery of the chip, between the plurality of pads (90) and between the plurality of pads and the block area (91), In (5), by dividing the top surface of the semiconductor chip (1) into a large number of mats of substantially the same size, and accommodating a plurality of electronic circuit blocks with different functions in one or more integer number of mats, It is something to be solved.

(E) Function According to the present invention, a plurality of pads of the electronic circuit block are provided for each block region, and a protective diode is formed between the block region and the plurality of pads and by using the region below the pads. Therefore, the pattern arrangement in the block area can be laid out in an orderly manner with almost no influence. On the other hand, by dividing the top surface of the semiconductor chip (1) into a large number of mats of substantially the same size along the partition line (5) and accommodating a plurality of electronic circuit blocks with different functions within an integral number of mats, the electronic circuit It becomes possible to design each block, and to divide an electronic circuit block into a fixed number of elements to design each mat. Therefore, parallel design can be performed by dividing each electronic circuit block, and the design period can be significantly shortened. Furthermore, since circuit changes can be made for each electronic circuit block and for each mat, there is no need to change the design of the entire IC.

(f) Examples The present invention will be explained in detail below. The present invention has similar effects on a semiconductor integrated circuit as shown in FIG. 8 and a semiconductor integrated circuit as shown in FIG. 3 using mat division. Therefore, the semiconductor integrated circuit described here uses mat division.

First, mat division will be explained below with reference to FIG. 3.

The top surface of the semiconductor chip (1) is divided into first and second regions (3>, (4)) having substantially the same shape using a dividing region (2) indicated by a two-dot chain line, Each area (
3) and (4) are divided into A-J, and -T mats. The mats A-J and -T are separated by partition lines (5) in which a power supply line indicated by a solid line and a ground line indicated by a dashed line extend adjacent to each other in parallel.

The arrangement of the power supply lines and ground lines forming the partition line (5) is such that the power supply line shown by a solid line is provided on the left side of each mat AJ and -T, and the ground line shown with a dashed line is provided on the right side. Therefore, only the partition lines (5) at both ends are formed of either the power supply line or the ground line, and the middle partition line is formed of both. Power lines and ground lines adjacent to each mat A-J, to T are integrated in each mat, and supply power to the circuit blocks.

In addition, the power line and ground line of each division line (5) are the third power line (6) and the second power line (7), the third ground line (8) and the second line shown by the three-dot chain line. The third and second power lines (6) and (7) are connected to the ground line (9) in a comb-teeth pattern, respectively, facing each other.
and the third and second ground lines (8), (
9) is the power supply pad Vcc1. among the pads provided around the pellet. V(H(2 and ground pad G
It is guided by NDI and GND2.

As will become clear later, due to the circuit, ~M on the mat is
Apart from these pads, vo. 8 r vcc41G
ND3, GND4 are used, and each power line, ground line, and second and third power lines (7
), (6), second and third ground lines (9
).

(8) is basically realized by one layer of two-layer wiring.

Each mat A-J divided by the above-mentioned division line (5>
, to-T are formed into shapes of substantially the same size;
Specifically, the width is set so that NPN l-rangisters can be lined up, and the length is set so that a certain number of elements can be laid out, for example, about 100 elements, which is easy to design. The size of this mat can be arbitrarily selected depending on the number of elements that can be easily designed depending on the electronic circuit block to be integrated.

The circuit elements integrated within the mat are composed of transistors, diodes, resistors, and capacitors, and are separated by normal PN isolation, and the connections of each element are connected by the first electrode layer of the two-layer wiring. Generally, there is crossover at the second layer of electrodes.

Next, with reference to FIGS. 4A and 4B, the circuit elements integrated within the mat and the partition lines (5) will be specifically described.

FIG. 4A is an enlarged top view of the vicinity of mat B.

The division line (6) indicated by the dashed line on the left is the division line (5) provided between mat A and mat B, and the division line (7> indicated by the dashed dot line on the right) is the division line (5) provided between mat A and mat B. A partition line (5>) is provided between the partition lines (6) and (7), and a transistor (8), a diode (9), and a resistor (shown by dotted lines) are connected between the partition lines (6) and (7).
10) and a capacitor (11) are integrated. Although these elements are shown sparsely in the drawing, they are actually densely integrated. In addition, the wiring between elements within the mat is -
The first electrode layer (12) shown by the dotted line is substantially completely formed, and the wiring between the mats A and B and between the mats B and C, such as signal lines and feedback lines, is formed in the second layer shown by the solid line. It is formed of the second electrode layer (13). These first and second electrode layers (12) and (13) are connected through contact regions indicated by x marks.

FIG. 4B is a sectional view taken along line AA' in FIG. 4A. An N-type epitaxial layer (15) is laminated on a P-type semiconductor substrate (14), and this epitaxial layer (
15) P+ reaching the semiconductor substrate (14) from the surface
A mold isolation region (16) is formed and a number of island regions are formed. In this island region (17), an NPN transistor (8), a diode (9), a resistor (10), a capacitor (11), etc. are made, and the collector region (18) of the NPN transistor (8) and the An N1 type buried region (19) is formed between the semiconductor substrate (14) and the epitaxial layer (14).
5) A silicon oxide film (
20) is formed, and a first electrode layer (12) is formed on this silicon oxide film (20). In addition, for example, FI is applied so as to cover this first electrode layer (12).
An insulating film (21) such as X is formed, and this insulating film (21)
A second electrode layer (13) is formed thereon. In addition, the power line (22) and ground line (23) are
Provided on the isolation region (16) and connected to the ground line (
23) is in ohmic contact with this isolation region (16) to stabilize the substrate potential.

More specifically, ten mats A-J are formed in the first region (3), ten mats N-T are formed in the second region 'vc<a>, The mats are arranged in substantially the same space in which about 100 elements can be integrated, and the mats are separated by partition lines (5).

The 20 mats listed above contain AM/FM as shown in Figure 6.
A 1-step IC for a stereo tuner is formed. 6th
The figure is a block diagram explaining this electronic block circuit, and includes an FM front end block (24), an FM-IF
block (25), noise canceller block (26)
), multiplex decoder block (27), A
It is composed of a total of five electronic circuit blocks including an M tuner block (28). Although each circuit block is well known, its function will be briefly explained.

First, the FM front end block (24) is a channel selection part for FM broadcasting, and receives an FM broadcasting signal of several tens of MHz to several hundred MHz, and frequency-converts it to an intermediate frequency signal of 10.7MHz. Since the number of elements is about 250, they are integrated into a -M mat. Next, FM-I
The F block (25) amplifies this intermediate frequency signal,
Thereafter, the signal is detected to obtain an audio signal, and since the number of elements is about 430, they are integrated on mats E to E. Next is the noise canceller block (26
) removes pulse noise such as ignition noise, and has approximately 270 elements, which are integrated into an NP mat. Furthermore, the multiplex decoder block (27) is a block that demodulates a stereo signal, and has about 390 elements, so the Q-T
are accumulated on the mat. Finally, the AM tuner block (28) is the channel selection part for AM broadcasting, and transmits the AM broadcast signal received by the antenna to an intermediate frequency (450KH2).
, and detects it to obtain audio output.
Since it has about 350 elements, it is integrated in A-D mats.

Furthermore, in FIG. 7 A1, FIG. 7 B, and FIG. 7 C,
A diagram in which a tuner block (28), a front end block (24), an FM-IF block (25), and a multiplex decoder block (27) are further divided into blocks is shown.

First, the local oscillation circuit (OS C') (29) in the AM tuner block (28) in FIG. 7A is connected to mat A, the mixing circuit (MI AGC) (31), high frequency amplifier circuit (R
F) (32) and intermediate frequency amplifier circuit (IF) (33)
is integrated into the mat C, a detection circuit (D ET ) (34) is substantially integrated into the mat D, and the power supply pad V as shown in FIG. The third power supply line (35), (36>, (37
), (38) to the first power supply line (39) of the mats A to D. It supplies C. In addition, the ground pad GNDI is connected to one end of the divided area (
2) Second ground line (41) shown by the three-dot chain line above
, (42), (43), and the respective second
The ground lines of (41), (42), (43
) are connected to the first ground line (44) of the mats A-D.

Next, the high frequency amplification circuit (45) and mixing circuit 4 in Figure 7B.
6〉 and a local oscillation circuit (47), the front end block (24〉) handles extremely small level signals of a few μ■, so it is difficult to use with other circuit blocks, especially FM-I.
It dislikes interference from the F block (25), and the local oscillation circuit (47) in this block oscillates itself, generating unnecessary radiation. Therefore, it should be separated from the FM-IF block (25) in particular, and a separate power supply (2) should be provided since the O8C block hates interference the most. C8, VCC4+GND3, G
ND4 is used.

In other words, it is integrated on the -M mat diagonally with the Flu-IF block (25), and the local oscillation circuit (47) is integrated on the mat K which is the most corner. A first power line (48) and a ground line (49) are provided through the M mat.
Through these, respective first power and ground lines (50) and (51) are provided.

On the other hand, the FM-IF block (25), which is composed of an intermediate frequency amplification circuit (52), a detection circuit (53), an S meter (54), etc., is integrated on the E-I mat, and the detection circuit (
53) is substantially integrated into the mat I, the S meter (54>, etc. is integrated into the mat G, and furthermore, the limiter circuit, mute circuit, etc. in the intermediate frequency amplification circuit (52) are substantially integrated into the mats E, F, and G. ing.

Here, a limiter circuit with an extremely high gain of 80 to 100 dB, a detection circuit (53) with a large signal level, the limiter circuit and an S meter (54) with a large signal level generate oscillation due to feedback, and the detection circuit (53) and S meter (54) have a high signal level. Meter (54
), the characteristics deteriorate due to mutual interference, so matte E,
The first power line (55) of F and G is connected to the third power line (37) shown by the three-dot chain line in the tree, and the first power line (56) of mats H and I is connected to one line. Third power line (
36). Further, the mat J is one in which an optional circuit provided by the user is integrated, and this first power supply line (57) is also connected to one third power supply line (35).

Also, the first ground line (58) shown by the dashed line on the E-J mat extends from the ground pad GNDI in a kite-like shape and is connected at one end to the second ground line (41), (42). , (43) are connected in the same manner as described above.

Next, the DC amplifier circuit (59) and decoder circuit (6) of the multiplex decoder block (27) in FIG.
0), the lamp driver circuit (61) is connected to mat Q and mat R, and the phase comparison circuit (62), low-pass filter circuit (63), voltage controlled oscillator (64), frequency dividing circuit (65), etc. are connected to mat S. It is substantially accumulated on the mat T. Also a power pad ■. The three electrodes (66), (67), and (68) extended from o2 in an octopus shape are as follows:
It passes between the AM tuner block (28) and the FM-IF block (25) and is connected at one end to the second power supply lines (69), (70), (71) on the divided area (2). Then, one goes to mats Q and R, one goes to mats S and T, and one goes to the noise canceller block (
26), which extends to the N-P mat.

On the other hand, the ground pad GND2 has three third
The ground lines of (72), (73), (74
), and as before, the N-P mat, Q, R
mat, S and T mats.

In addition, Bad V is used to prevent mutual interference between blocks.
ccs + Vccz, bad GNDI, GND2
Use the pads Vccs + VCC! separately. is connected to lead (75), pad GNDI, GN
D2 is connected to lead (76). This directly changes the fluctuation of bad v0゜1 to pad VCC! By using two thin metal wires, the impedance of the thin metal wires is lowered. Therefore, pulse noise or the like that enters the lead cannot be amplified through the impedance, and voltage fluctuations can be prevented.

As explained above, the division line (5) consisting of the first power supply line and the first ground line is divided into A-J,
-T mats are divided. In addition, since the first power supply line and the first ground line are formed substantially in a comb-like shape, the space between the mats and the surrounding space can be effectively utilized, and the pads Vcc+ around the chip (1)
, GNDI, and GND2 can be connected over the shortest distance.

Next, countermeasures against interference between the FM front end (24) and the FM-IF block (25) will be described. Previously, individual I
This was a problem with the set board because C was used for each, but this time, since it was made into one chip, this interference became an additional problem, but it was solved by the following measures.

First, as mentioned above, the FM front end block (24
) handles extremely small level signals of several μ■,
It dislikes interference from other circuit blocks, especially the FM-IF block (25), and the local oscillation circuit (47) configured within this block oscillates itself and generates unnecessary radiation, so it is not compatible with other blocks. It is necessary to separate it or provide a separate power source.

For these reasons, first, the FM front end block and the FM-IF block were provided diagonally, and the local oscillation circuits in these blocks were integrated on the mat K and separated from each other. Next, AM tuner block (28) and FM-I
F block (25), FM front end block (2
4) and the noise canceller block (26), that is, by widening the partition line width between mat D, mat E, mat M, and mat N, the FM front end block (24) can be easily connected to other blocks, especially the FM-IF block ( 25
). Also, between mat D and mat E, and between mat M and mat N, there is a power pad VCC! The electrodes (66) and (67) extend further to the second region (4).
), (68) and an electrode (40) extending from the ground pad GNDI to the first region (3), and furthermore, second power lines (69), (7) are provided on the divided region (2).
0), (71) and the second ground line (41)
, (42), and (43) are provided. Therefore, F.M.
The front end block (24) is connected to the adjacent FM-I
F block (25), AM tuner block (28)
and the noise canceller block (26), especially the power lines (66), (67), (68
) prevents unnecessary radiation, and since at least one of the ground lines (40) is in direct contact with the isolation region (16), substrate current can be sucked out and interference is prevented.

Also, since the local oscillation circuit (47) in this FM front end block (24) dislikes interference, the power pad
. o4 and a ground pad GND4 are provided separately, and external circuits are supplied by a power supply pad VCCB and a ground pad GND3.

Furthermore, the FM-IF block (25>)
It has a limiter circuit for removing the M section, and this circuit is integrated with mat E and mat F.

The capacitor in this limiter circuit causes leakage to the substrate, and this leakage current flows to the FM front end, causing malfunction. Therefore, the capacitors are grouped together in the mat E, and the first ground line (77) of the division line (5) on the left side of the mat E is intensively sucked out. Furthermore, the first ground line (77) connects the FM-IF block (25) and the multiplex decoder block (25).
27> and the noise canceller block (26) are extended to the outer periphery of the area where the noise canceller block (26) is formed, and leakage current generated from these is also sucked out. Similarly, a ground line (78) is provided around the left half of the chip (1).

Also, due to wiring reasons, the third power line (35>, (3
6), (37), (38), second power supply line (69), (70), (7) on divided area (2)
1) and the second ground line (41), (42
), (43), etc., cross over via the through holes indicated by black circles and the second electrode layer (79) indicated by dotted lines. Especially the AM tuner block (2
8) does not operate simultaneously with the external block circuit, so AM
Tuner block (28) and FM-IF block (2
5) One pad V. cl is shared, so there is a crossover. Also Grand Bad GNDI
The same is true.

The above-mentioned configuration is shown in FIG. -The one indicated by the dotted chain line is 1
Among the electrodes formed in each layer, the one shown by a solid line is the second layer electrode. The area indicated by the X mark is the through hole. Also, since the two blocks do not work at the same time, the power line and ground line are shared, and the pattern is
. . Since the electrodes from 1 and GNDI to the through hole are shared, the area occupied by the electrodes can be reduced.

Let us take an example of the features of the present invention. For example, if you don't need the AM tuner block (28), use the A-D mat.
4 which becomes multiple breech decoater flock (27)
For example, mats I and J are integrated on the remaining mats Q and R. Therefore I, J
, S, and T are redundant, so by deleting these mats, the mats can be arranged neatly in a rectangular chip. Here, the first layer wiring within the mat can be used as is, and only the wiring between mats and the wiring between blocks need be considered.

Also, when partially improving the FM-IF block (25),
For example, it is only necessary to take out the mat F, which is the improved part, and improve it, and the other mats E, G, and H can be used as they are. Also, when adding another block that is an option for the user, all the mats can be used as is and only the necessary number of mats can be added to this block, and in this case mat J is used as the mat for this option.

In other words, since mats of the same size are formed in a matrix, replacement, addition, and deletion are very easy.

The above is the configuration of mat division. Next, the configuration of protection against surges of the present application will be described.

Basically, the configuration is as shown in the circuit diagram shown in FIG. 1st
The figure shows how this circuit is constructed.

Pads (90)...(90) provided around the semiconductor chip (1) and used for input/output signals are provided around the semiconductor chip (1) for each electronic circuit block. For example, mat A that becomes the AM tuner block (28)
In the block area (91) of the mat D, a total of 11 pads (90) (90) are provided on the left side and the upper side of this block area (91). From now on, for convenience of explanation, the entire area in which electronic circuit blocks are formed will be named a block area.

As you can see from Figures 3 and 5, the pad (90)...
・(90) and third power line (35), (36)
, (37), and (38), nothing is formed in the lower substrates, which are substantially wasteful areas. Therefore, in the present application, an N-type first diffusion region (
92), an N-type second diffusion region (93) is provided below the pads (90)...(90), and an N-type second diffusion region (93) is provided in the N-type first diffusion region (92>). , eleven P-type third diffusion regions (94) were provided corresponding to each pad.

The first to third diffusion regions (92), (93)
, (94) are the cathode of the diode Dl, the cathode of the diode D, and the diode D1 in FIG. 10, respectively.
It becomes an anode. Here, the anode of the diode D2 is a P-type semiconductor substrate.

FIG. 2A is a partially enlarged top view of the block area (91) of the AM tuner block in FIG.
, (36) is shown in more detail.

(92), (93), and (94) indicated by dotted lines are the first to third diffusion regions, respectively, and (35) and (36) indicated by dashed-dotted lines are the third power supply lines.

In the second diffusion region (93), there is an N+ region indicated by a dotted line.
There is a contact area (95) of the type, and there is a first electrode (96) shown in dashed lines extending through this contact area (95) to said third diffusion area (94). One end of this first electrode (96) is connected to a pad (
90) is formed, and a second wire #A (97) shown by a solid line is formed at the other end to be connected to the electronic circuit block. The X marks for (98), (99), and (100) are
contact between the first electrode (96) and the pad (90);
The contact between the third diffusion region (94) and the first electrode (96) and the contact between the first electrode (96) and the second electrode (97) are shown. And the x mark in (101) is
A contact between the third power supply line (35) and the first diffusion region (92) is shown. Also shown with a dotted line (102
) is an N-type dummy island surrounding the N-type second region (93).

Next, a second cross-sectional view taken along line A-A' in FIG.
This will be explained using Figure B.

An N-type epitaxial layer (15) is laminated on a P-type semiconductor substrate (14), and a P+ type separation layer reaches the semiconductor substrate (14) via this N-type epitaxial layer (15). There is a region (16). Surrounded by this separation region (16) are first and second diffusion regions (9).
2), (93) and a dummy island (102) are formed.

Fig. 2C shows the pad (9o) corresponding to mat N-P.
・(90) and the third ground line (72), (7
3) and (74). Basically, it is the same as FIG. 2A, but a part of the first diffusion region (92) protrudes into the block region and contacts the first power supply line with the contact (103) indicated by the X mark. There is.

(g) Effects of the invention As is clear from the above explanation, the first effect is the pad (90).
... (90) The structure shown in FIG. 10 can be achieved by effectively utilizing the space between the pad group and the power supply line or ground line, and a part of the power supply line or ground line. Furthermore, one first diffusion region (92) is provided for each block region.

Therefore, even if noise enters the first diffusion region, only this block region is interfered with, and other block regions are hardly affected. Therefore, it is effective as a measure to prevent mutual interference between blocks.

Furthermore, since a protection diode can be formed around the outer periphery of the block region, the pattern arrangement of the block region can be laid out in an orderly manner with little influence.

Second, around the N-type second diffusion region (93),
N-type dummy island (102) surrounded by isolation regions
By providing this, it is possible to prevent the parasitic silage operation caused by the second diffusion region (93) and the first diffusion region (92). Therefore, destruction caused by parasitic silicon risk operation can be prevented. Here, the circuit elements connected to the power supply line VCC can be protected from destruction.

Thirdly, since the power supply line, the first electrode, and the second electrode can be extended over the first diffusion region (92), this first diffusion region can be effectively utilized, and the chip area can be reduced. Increase can be prevented.

Fourth, if the top surface of the semiconductor chip (1) is divided into a large number of mats of substantially the same size along the partition line (5), and a plurality of electronic circuit blocks with different functions are accommodated in an integral number of mats, the electronic circuit blocks Each project can be designed in parallel, significantly shortening the design period.

Furthermore, since the electronic circuit block can be divided into a fixed number of elements and designed for each mat, parallel design for each mat can be performed.

Further, since circuit changes such as deletion, addition, and modification can be designed for each electronic circuit block or each block, it is sufficient to make changes for each block or each mat, and there is no need to change the design of the entire IC.

Furthermore, mats can be made into cells as basic blocks, so
Once the design is complete, when changing the circuit afterwards, you only have to modify the mat to be changed, and the other mats can be used as they are, resulting in extremely high reliability.

Moreover, since the structure is divided into mats, the lower layer of the third power supply line and the third ground line can be used effectively. The connection between the first diffusion region (92) and the power supply line is such that the power supply line is connected between the pad (90)...(90) and the block region in the upper half of the chip, and the power supply line is connected to the block region in the lower half of the chip. Since the first power supply line extends to the lower end of the area, connection can be easily made without providing a new power supply line. In addition, the following measures are taken to avoid mutual interference between electronic circuit blocks. A first diffusion region is provided for each block region. This has the advantage that even if noise enters the first diffusion region of a certain block, the noise will not enter other blocks because each block is separated. On the other hand, if the first diffusion region is provided separately for each pad, this effect will be further improved, but the connection with the power supply line will become very complicated. Therefore, providing each block has the advantage of reducing the number of connections to power supply lines and preventing interference with other blocks.

Further, since the first diffusion region is formed surrounding the area where the mat A-J and the mat -T are formed, it is possible to prevent noise from entering from around the chip.

[Brief explanation of the drawing]

1 is a top view illustrating the formation position of the protection diode in the semiconductor integrated circuit of the present invention, FIG. 2A is a partially enlarged view of the protection diode in FIG. 1, and FIG. 2B is the same as in FIG. A-
2C is a partially enlarged view of the protection diode in FIG. 1, FIG. 3 is a top view showing the semiconductor integrated circuit of the present invention, and FIG. 4A is a cross-sectional view taken along line A'. FIG. 4B is a top view showing the matte area, FIG. 4B is a sectional view taken along the line AA' in FIG. 4A, FIG. 5 is a top view showing the electrode pattern of the semiconductor integrated circuit of the present invention, and FIG. 7A is a diagram explaining the AM tuner block, FIG. 7B is a diagram explaining the FM front end block and FM-IF block, and FIG. 7C is a block diagram of the electronic circuit incorporated in the semiconductor integrated circuit of 8 is a top view of a conventional semiconductor integrated circuit, FIG. 9 is a sectional view between block b and block C in FIG. 8, and FIG. 10 is a diagram illustrating the structure of a protection diode. FIG. (1)...Semiconductor chip, (2)...Divided area,
(3)...first area, (4>...second area, (5>...division line, (35), (36)
), (37), (3B>...Third power supply line, (41), (42), (43)...Second ground line, (69), (70),
(71)...Second power line, (72), (
73), (74)...Third ground line,
(90)...Pad, (91)...Block area, (92)...First diffusion area, <93)...
・Second diffusion region, (94)...third diffusion region,
(96)...first electrode, (97)...second electrode, (102)...dummy island.

Claims (8)

[Claims] (1) An electronic circuit area in which an electronic circuit is formed on substantially the entire surface of a semiconductor chip, a block area in which a plurality of electronic circuit blocks having different functions constituting the electronic circuit are formed in this electronic circuit area, and the semiconductor chip a plurality of pads formed on the sides of a block region corresponding to the periphery of the chip and led out from the electronic circuit block; and a first diffusion of one conductivity type formed between the block region and the plurality of pads. and a second diffusion region of one conductivity type provided under the plurality of pads, respectively corresponding to the plurality of pads,
a third region of opposite conductivity type formed in the first diffusion region; a first electrode connecting the second diffusion region and the third diffusion region; A semiconductor integrated circuit comprising: a second electrode connected to an electronic circuit block; and a power supply line connected to the first diffusion region. (2) A dummy island region of one conductivity type surrounded by an isolation region is provided around the second diffusion region.
Semiconductor integrated circuit described in Section 1. (3) The semiconductor integrated circuit according to claim 1, wherein the power supply line is formed on the first diffusion region. (4) The semiconductor integrated circuit according to claim 3, wherein the power supply line is formed in a first layer, and the second electrode is formed in a second layer. (5) A semiconductor chip is formed by dividing a semiconductor chip into a plurality of regions of substantially the same size by arranging a plurality of division lines in the same direction, each of which is a set of power supply lines and ground lines extending adjacent to each other. a mat, an electronic circuit composed of a plurality of electronic circuit blocks with different functions incorporated in an integral number of mats of the semiconductor chip, and a block area corresponding to the periphery of the semiconductor chip and in which the electronic circuit block is formed. a plurality of pads formed on a side and led out from the electronic circuit block; a first diffusion region of one conductivity type formed between the block region and the plurality of pads; and a layer below the plurality of pads. A second conductivity type provided in
a third region of an opposite conductivity type formed in the first diffusion region corresponding to each of the plurality of pads, and the second diffusion region and the third diffusion region. It includes a first electrode, a second electrode connecting the first electrode and the electronic circuit block, and a third electrode connecting the first diffusion region and extending to the power supply line. A semiconductor integrated circuit characterized by: (6) A dummy island region of one conductivity type surrounded by an isolation region is provided around the second diffusion region.
Semiconductor integrated circuit described in Section 1. (7) The semiconductor integrated circuit according to claim 5, wherein the third electrode is formed on the first diffusion region. (8) The third electrode is formed in the first layer, and the third electrode is formed in the second layer.
8. The semiconductor integrated circuit according to claim 7, wherein the electrode is formed in the second layer.