JPH0223662A - Semiconductor integrated circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

Detailed Description of the Invention (A) Industrial Application Field The present invention relates to a semiconductor integrated circuit, and in particular to a semiconductor integrated circuit having an FM front-end block and an FM-IF block, and more particularly, to a semiconductor integrated circuit having an FM front-end block and an FM-IF block. This invention relates to a semiconductor integrated circuit having a pattern layout that allows easy model development.

(b) Conventional technology in general is disclosed in Japanese Patent Application Laid-Open No. 59-84542 (HOI L
21/76), a semiconductor integrated circuit technology in which a plurality of circuit blocks are formed on the same semiconductor substrate has the configuration shown in FIG.

FIG. 8 is a schematic plan view of the semiconductor chip (101), and a to f indicate circuit blocks. These circuit blocks handle different frequencies and signal levels, and
The functions are also different.

This circuit block is formed in an N-type region (103) on a P- type semiconductor substrate (102) as shown in FIG. 9, and each circuit block is formed in a highly doped P+-type region ( 104). Here, block b and block C are shown.

The P+ type area (104) for this division has one end connected to P
It is in contact with a - type semiconductor substrate (102), and the other end is ohmink-connected to a ground line (106) through an oxide film (105) on the semiconductor surface.

A ground line (106) is gathered from each block to the center of the integrated circuit and extends to the ground bonding pad GND at the left end.

Next, as shown in FIG. 8, the power lines (Vcc) of each block circuit are grouped around the outer periphery of the integrated circuit and individually connected to power supply bonding pads.

On the other hand, since the circuit blocks a to f have different functions, the number of elements present in each block is different, and the block sizes are different.

(c) Problems to be Solved by the Invention In the semiconductor integrated circuit consisting of the plurality of blocks described above, the FM stereo tuner circuit has a gold circuit.
When the front-end block and the FM-IF block were integrated, malfunctions occurred due to interference between the two blocks, making it difficult to integrate them into a single chip. In addition, since the sizes of circuit blocks a to f are different, in order to efficiently fit all of these circuit blocks into the semiconductor chip (101), the sizes of each circuit block work together, and the size of each circuit block must work together to fit all the circuit blocks into the same chip. There was a problem that made it difficult to accumulate.

Also, if you delete circuit block a and insert another circuit block a' with improved characteristics, or if you try to add circuit block g with another function to the circuit block configuration of Figure 8 = 4-. , since the size of each block was different, it was necessary to recreate all the patterns.

Therefore, in recent years, the lifespan of products has become extremely short, and when a user tries to incorporate a unique circuit desired by a chip into a certain chip, even though the user wants a short delivery time, the circuit The problem was that it required a very long lead time to remake the pattern.

(2) Means for Solving the Problems The present invention has been developed in view of the problems described above, and includes:
This problem was solved by providing a suction electrode that absorbs leakage current from the semiconductor substrate, and also by dividing the top surface of the semiconductor chip (1) into a large number of mats of substantially the same size at the partition line (5), which have multiple mats with different functions. The conventional problem is solved by housing electronic circuit blocks within one or more integral number of mats.

(E) Function According to the present invention, the side of the FM-IF block, which is the FM front end block side, becomes a path for the leakage current that enters the FM front end block. 43) and (79) are provided to intensively suck out the leakage current and prevent it from interfering with the FM front end block. In addition, by dividing the top surface of the semiconductor chip (1) into a large number of mats of substantially the same size along the partition line (5) and accommodating a plurality of electronic circuit blocks with different functions within an integral number of mats, the electronic circuit block In addition, by dividing the electronic circuit block into a fixed number of elements, it becomes possible to design each mat. Therefore, parallel design can be performed by dividing each electronic circuit block, and the design period can be significantly shortened. Furthermore, since circuit changes can be made for each electronic circuit block and for each mat, there is no need to change the design of the entire IC.

(F) Embodiment First, a first embodiment of the present invention will be described in detail with reference to FIG. For convenience of explanation, the structure of mat division, which is one of the features of the present invention, will be explained here, so the structure of mat division will be described first.

The upper surface of the semiconductor chip (1) is divided into divided regions (2) indicated by two-dot chain lines.
) is used to divide the area into first and second areas (3) and (4) with substantially the same shape, and separate each area (3) into two.
, (4) is divided into A-J, and -T mats. The mats A-J and -T are separated by partition lines (5) in which a power supply line indicated by a solid line and a ground line indicated by a dashed-dotted line extend adjacently and in parallel.

Regarding the arrangement of the power supply lines and ground lines forming the partition line (5), a power supply line shown by a solid line is provided on the left side of -T in each mat AJ, and a ground line shown with a dashed line is provided on the right side. Therefore, the partition lines at both ends (5)
Only one line is formed as either the power supply line or the ground line, and the middle partition line consists of both. Each mat A-J.

The power line and ground line adjacent to K-T are
It is integrated into each mat and supplies power to the circuit blocks.

In addition, the power line and ground line of each division line (5) are the third power line (6) and the second power line (7), the third ground line (8) and the second line shown by the three-dot chain line. The third and second power supply lines (6), (7) and the third and second ground lines (8), (9) are connected to the ground line (9) in a comb-teeth pattern, facing each other.
is the power pad ■ inside the pad provided around the pellet. CI + VCCI and Grandborough)? GN
D1, guided by GND2.

As will become clear later, due to the circuit, ~M on the mat is
Apart from these pads, vccs l VCC4+G
ND3, GND4 are used, and each power line, ground line, and second and third power lines (7
), (6), second and third ground lines (9
).

(8) is basically realized by one layer of two-layer wiring.

Each mat A-J divided by the above-mentioned division line (5)
, to-T are formed into shapes of substantially the same size;
Specifically, the width is set so that six NPN transistors can be lined up, and the length is set so that a certain number of elements can be laid out, for example, about 100 elements, which is easy to design. The thickness of this mat can be arbitrarily selected depending on the number of elements that can be easily designed depending on the electronic circuit block to be integrated.

The circuit elements integrated within the mat are composed of transistors, diodes, resistors, and capacitors, and are separated by normal PN isolation, and the connections of each element are connected by the first electrode layer of the two-layer wiring. Generally, there is crossover at the second layer of electrodes.

Next, with reference to FIGS. 2A and 2B, the circuit elements integrated within the mat and the partition lines (5) will be specifically described.

FIG. 2A is an enlarged top view of the vicinity of mat B.

The division line (6) indicated by the dashed line on the left is the division line (5) provided between mat A and mat B, and the division line (7) indicated by the dashed dot line on the right is the division line (5) provided between mat B and mat B. A transistor (1o), a diode (11), a resistor (1
2> and a capacitor (13) are integrated. Although these elements are shown sparsely in the drawing, they are actually densely integrated. Further, wiring between elements within a mat is substantially formed by the first electrode layer (14) shown by a dashed line, and wiring between mats A and B, and between mats B and C, e.g. A signal line and a feedback line are formed of a second electrode layer (15) shown by a solid line. These first and second electrode layers (14) and (15) are connected through contact regions indicated by x marks.

FIG. 2B is a sectional view taken along line AA' in FIG. 2A. An N-type epitaxial layer (17) is laminated on a P-type semiconductor substrate (16), and this epitaxial layer (
17) P+ reaching the semiconductor substrate (16) from the surface
A mold isolation region (18) is formed and a number of island regions are formed. Inside this island region (19) are an NPN transistor (10) and a diode (11).
, a resistor (12), a capacitor (13), etc. are made, and the collector region of the NPN transistor (10) (
An N+ type buried region (21) is formed between the semiconductor substrate (16) and the semiconductor substrate (16). A silicon oxide film (22) is formed on the surface of the epitaxial layer (17) by, for example, a CVD method.
), a first electrode layer (14) is formed. Further, an insulating film (23) such as PIX is formed to cover this first electrode layer (14), and a second electrode layer (15) is formed on this insulating film (23). has been done. Also, the power line (24) and the ground line (24)
5> is provided on the isolation region (18), and the ground line (25) is in ohmink contact with this isolation region (18) to stabilize the substrate potential.

More specifically, as shown in FIG.
10 mats of -J are formed, and 10 mats of -T are formed in the second region (4), so that the mats are in substantially the same space where about 100 elements can be integrated, and the space between each mat is It is divided by division lines (5).

The 20 mats listed above contain AM/FM as shown in Figure 3.
A 1-chip stereo tuner IC is formed. Third
The figure is a block diagram explaining this electronic block circuit, and includes an FM front end block (26), an FM-I F
block (27), noise canceller block (28)
), multiplex decoder block (29), A
It is composed of a total of five electronic circuit blocks including an M tuner block (30). Although each circuit block is well known, its function will be briefly explained.

First, the FM front end block (26>) is the FM broadcast channel selection part, which receives the FM broadcast signal of several tens of MHz to several hundred MHz and converts it into an intermediate frequency signal of 10.7 MHz. Since the number of elements is about 250, they are integrated into a -M mat. Next, FM-I
The F block (27) amplifies this intermediate frequency signal and then detects it to obtain an audio signal, and has about 430 elements, so it is integrated on the E-I mat. Next is the noise canceller block (28)
is a device that removes pulse noise such as Ibnira-12= John noise, and has a power of about 2
Since it has 70 elements, it is integrated into an NNP mat. Furthermore, the multiplex decoder block (29
) is a block for stereo demodulating stereo signals, and since it has approximately 390 elements, it is integrated into a QT mat. Finally, AM tuner block (30)
is the channel selection part of AM broadcasting, and is the AM broadcast received by the antenna.
It converts a broadcast signal to an intermediate frequency (450 KHz>) and detects it to obtain an audio output. It has about 350 elements and is integrated into A-D mats.

Furthermore, in FIG. 4A, FIG. 4B, and FIG. 4C, AM
A diagram in which a tuner block (30), a front end block (26), an FM-IF block (27>), and a multiplex decoder block (29) are further divided into blocks is shown.

First, the local oscillation circuit (OS C) (31) in the AM tuner block (30) in FIG. 4A is connected to Matsu) A, the mixing circuit (MI A G C) (33), high frequency amplification circuit (RF) (34) and intermediate frequency amplification circuit (I F'
) (35) is connected to mat C, and the detection circuit (DET) (36
) are substantially integrated in the mat D, and as shown in FIG. 1, the third power supply lines (37) , (38> , (
39), V to the first power supply line (41) of the mats A to D via (40). 0 is supplied. In addition, the ground pad GND 1 connects to the second ground line (shown by the three-dot chain line) on the one end divided region (2) via the three octopus-shaped electrodes (42) provided between the mat M and the mat N.
43), (44), (45).

(46), and the respective second ground lines (4
3), (44), (45), (46) are A
- It is connected to the first ground line (47) of the mat of D.

Next, the high frequency amplification circuit (48) and mixing circuit (48) in Figure 4B are shown.
9) and a local oscillation circuit (50), the front end block (26>), which is composed of a local oscillation circuit (50), handles signals at an extremely small level of several μV, so it
It dislikes interference from the F block (27), and the local oscillation circuit (50) in this block oscillates itself, generating unnecessary radiation. Therefore, the FM-IF block (27) and the OSC block (50) are separated from each other, and since the OSC block (50) hates interference the most, a separate power supply V is provided. cs.

V, c4. GND3 and GND4 are used.

That is, the local oscillation circuit (5o) is integrated on the mat K located diagonally with the FM-IF block (27), and the local oscillation circuit (5o) is integrated on the mat K, which is the most corner. A first power supply line (51) and a gelland line (52) are provided through GND4. In addition, the mat of M is VCC8 and GND3.
Through these, respective first power supply lines and ground lines (S3), (54) are provided.

On the other hand, the FM-IF block (27), which is composed of an intermediate frequency amplification circuit (55), a detection circuit (56), an S meter (57), etc., is integrated on the E-I mat, and the detection circuit (56) is on mat I, S meter (57) etc. is on mat G
Furthermore, a limiter circuit, a mute circuit, etc. in the intermediate frequency amplification circuit (55) are substantially integrated in the E, F, and G matte circuits.

Here, a limiter circuit with an extremely high gain of 80 to 100 dB and a detection circuit (56) with a high signal level, = 15, the limiter circuit and an S meter (57) with a high signal level.
> causes oscillation due to feedback, and the characteristics of the detection circuit (56) and S meter (57) deteriorate due to mutual interference, so the first power supply line (58) of mats E, F, and G is The mat H is connected to the third power line (39) shown by the dotted chain line
, I are connected to the third power line (38) of the tree. Mat J also integrates optional circuits provided by the user, and this first power line (6o) is also connected to one third power line (6o).
37).

Also, the first ground line (61) shown by the dashed line on the E-J mat extends from the ground pad GNDI in a kite-like shape and is connected at one end to the second ground line (43), (44> , (45> , (46)
and are connected in the same way as above.

Next, the DC amplifier circuit (62) and decoder circuit (6) of the multiplex decoder block (29) in FIG.
3), the lamp driver circuit (64) is connected to mat Q and mat R, and the phase comparator circuit (65), low-pass filter circuit (66), voltage controlled oscillator (67), dividing circuit (68), etc. are connected to mat S and mat T are substantially integrated.Also, from the power supply pad vccz, 3
Main extended electrodes (69), (70), (71
) is AM tuner block (3o) and FM-IF
The second power supply lines (72>, (73), (74) on the divided area (2) pass between the block (27) and the divided area (2).
One end is connected to. Then, one tree extends to mats Q and R, one extends to mats S and T, and one tree extends to the NNP mat, which becomes the Noise Kiln Cellar block (28).

On the other hand, the ground pad GND2 has three third
The ground lines of (75), (76), (77
), and as before, N-P mat, Q, H
mat, S and T mats.

Furthermore, pad V is used to prevent mutual interference between blocks.
cc+ *Vcc*, Bad GNDI, GND2
I used it for a minute each and used Bad V. CI+VCCI is connected to the lead, and BAD GND'l, GND2 is connected to the lead. First, the fluctuation of pad VCel is directly converted to pad V. C! By using two thin metal wires, the impedance of the thin metal wires is lowered. Therefore, pulse noise or the like that enters the lead is not amplified through the impedance, and voltage fluctuations can be prevented.

As explained above, A-J,
-T mats are divided. In addition, since the first power supply line and the first ground line are formed in a substantially comb-like shape, the space between the mats and the surrounding space can be effectively utilized, and the pad V around the chip (1), c1
．． GNDI and GND2 can be connected at the shortest distance.

Next, countermeasures against interference between the FM front end (26) and the FM-IF block (27) will be described. Previously, individual I
This was a problem with the set board because C was used for each, but this time, since it was made into one chip, this interference became an additional problem, but it was solved by the following measures.

First, as mentioned above, the FM front end block (26
) handles extremely small level signals of several μV, so
Because it dislikes interference from other circuit blocks, especially the FM-IF block (27), and because the local oscillation circuit (50) configured within this block oscillates itself and generates unnecessary radiation, it must be separated from other blocks. or provide a separate power source.

For these reasons, first, the FM front-end block (26) and the FM-IF block (27) were provided diagonally, and the local oscillation circuit (50) in this block was spaced apart to allow integration on the mat K. Next, between the AM tuner block (30) and the FM-IF block (27), the FM front end block (26) and the noise canceller block (28), that is, the matte D and the matte E1.
By widening the partition line width of mat M and mat N, F
The M front end block (26) is kept away from other blocks, especially the FM-IF block (27). Also, between mat D and mat E, and between mat M and mat N, there is a power pad ■. 0. An electrode (69) extending further into the second region (2).

(70), (71) and an electrode (42) extending from the ground pad GNDI to the first region (3),
Furthermore, a second power supply line (72) is provided on the divided area (2),
(73), (74) and the second ground line (4
3), (44), (45), and (46) are provided. Therefore, FM front end block26)
is separated from the adjacent FM-IF block (27), AM tuner block (30) and noise canceler block (28), and in particular the power line (69),
(70), (71) prevent unnecessary radiation, and ground lines (43>, (44>, (45),
At least one of (46) is in contact with the isolation region (18), so it can suck out the substrate current and prevent interference.

FIG. 5 shows the FM front end block (2) as described above.
6) is a diagram specifically showing a separated state of the FM-IF block (27). - The electrodes shown by dotted lines are the first to third power supply lines and the first to third ground lines formed in the first layer, and the electrodes shown by solid lines are for crossover lines formed in the second layer. This is the electrode.

Also, since the local oscillation circuit (50) in this FM front end block (26) dislikes interference, the power supply pad V
. o4 and a ground pad GND4 are provided separately, and the external circuit is supplied with a power supply pad V (os) and a ground pad GND3.

Furthermore, the FM-IF block (27)
This circuit is integrated with mat E and mat I-F.

Each MOS type capacitor in this limiter circuit is formed within an island, and the PN
The junction capacitor causes leakage to the board, and this leakage current flows to the FM front end, causing malfunction. Therefore, a dummy island (78) shown by hatching in FIG. 6 is provided. This dummy island (78
) consists of an N-type epitaxial layer (17) surrounded by a P"-type isolation region (18) connected to a semiconductor substrate (16) given a ground potential, so a barrier is formed by this PN junction. Therefore, it is possible to prevent leakage current from entering the FM front end block.Furthermore, the capacitors are bundled in the mat E, and the side of the FM-IF block corresponding to the area where the FM front end block is formed is Specifically, there are suction electrodes (43) and (79) on the left side and bottom side of mat E, which are hatched with the
) and a contact in the separation area to intensively suck out the water. In reality, since the capacitors are integrated in the mat E, the suction electrode (43) extends only to the lower side of the mat E.

However, when the capacitors are distributed among mats E to J, the electrodes shown at the bottom of mats E to J in Figure 1 (
43), and may be in contact with the isolation region (18) formed in the lower layer of this electrode over substantially the entire surface.Furthermore, the extraction electric current m(79)c, FM-I
(27), the multiplex decoder block (29) and the noise canceller block (28) are extended to the outer periphery of the area where they can be formed, and the leakage current generated from these is also absorbed.Similarly, the chip A ground line (80) is also provided around the left half of (1). Also, due to wiring reasons, a third power line (37
), (38), (39), <40), second power line (72), (73) on divided area (2)
) , <74) and the second ground line (43)
, (44), (45), (46), etc. are through poles indicated by black circles (corresponding to the X marks in Figure 5).
There is crossover via the second electrode layer shown by the dotted line (corresponding to the solid line in FIG. 5). Especially A
Since the M tuner block (30) does not operate at the same time as the outside block circuit, the AM tuner block (30)
and FM-IF block (27) to one pad Vcc+
They share the same name, which is why they cross over. The same applies to the ground bad GND1.

Next, the mat E will be explained in further detail using enlarged views of FIG. 7A and FIG. 7B. The ground twin (81), (8
2), a ground line (81) and a suction electrode (83) arranged in a comb-teeth pattern.A partially enlarged view of this mat E is shown in FIG. 7A.

The thickest electrodes (81) and (82) shown with dashed lines
are the ground lines (79) and (43) formed on both sides of mat E in FIG. A MOS type capacitor (84) is formed between these two ground lines (81) and (82), and the hatched part corresponds to the upper electrode (85>) of the capacitor (23). This upper layer electrode (85) is in ohmic contact with the second layer electrode (86) via the contact indicated by the X mark on the right side. It extends to the right side and is connected to the circuit elements included in the present electronic circuit block.Contacts (87) indicated by X marks on the top and bottom or left and right sides of the upper layer electrode (85) are shown in FIG. 7B. A P-type diffusion region (88) formed in the lower layer of the upper layer electrode (85) shown and an electrode (89) corresponding to the lower layer electrode of the capacitor.
) shows the contact part. Here the electrode (89)
is hereinafter referred to as the lower layer electrode.

Similar to the upper layer electrode (85), this lower layer electrode (89) is connected to the second layer electrode (91) via a contact (90).
This second layer electrode (91) is extended to the right and is connected to a circuit element included in the present electronic circuit block.

Finally, let's take a look at an example of the features of the present invention. For example, if the AM tuner block (30) is not needed, the four mats that will become the multiplex decoder block (29) are directly integrated into the mats A to D, and the remaining mat Q
For example, matte and J are integrated in matte R and matte R. Therefore, since the I, J, S, T (7) mats are redundant, by deleting this mat, the mats can be arranged neatly in a rectangular chip. Here, the first layer wiring within the mat can be used as is, and only the wiring between mats and the wiring between blocks need be considered.

In addition, when partially improving the FM-IF block (27),
For example, it is only necessary to take out and improve the mat F, which is the improved portion, and the other mats E, G, and H can be used as they are. Also, when adding another block that is an option for the user, all the mats can be used as is and only the required number of mats can be added to this block, and in this case mat J is used as the mat for this option.

In other words, since mats of the same size are formed in a matrix, replacement, addition, and deletion are very easy.

(g) Effects of the invention As is clear from the above explanation, firstly, the FM-I which is the area side where the FM front end block is formed.
By providing suction electrodes (79) and (43) on the sides of the F block to suck up leakage current from the semiconductor substrate, it becomes possible to suck out leakage current generated from the region where the FM-IF block is formed. Therefore, FM-
The IF block and FM front end block can be integrated into one chip.

Second, connect the extraction electrode (79) directly to the ground pad GN.
When connected to D2 or the suction electrode (43) is connected to the ground line (42), the suction electrode (79),
The leakage current sucked out in (43) is GNDI, G
It becomes possible to flow to the outside via ND2.

Thirdly, by bringing the suction electrodes (79) and (43) into contact with the separation region provided in the lower layer of the electrode over substantially the entire surface, the separation region that serves as a leakage current suction port and the suction Electrodes (79) and (43) are FM
-It will surround the IF block.

Therefore, even if the capacitors are not integrated in the mat E but are dispersed, they can be effectively sucked out.

Fourth, the suction electrodes (79) and (80) are extended around the semiconductor chip, and the isolation region is defined as the semiconductor chip (1).
), it is possible to suck out the leakage current flowing to the surrounding area.

Fifth, by integrating the capacitors included in the FM-IF block in a specific area where this FM-IF block is formed and providing a suction electrode in this specific area, it is possible to eliminate the source of leakage current. It is possible to concentrate suction from the area where a certain capacitor is formed.

Sixth, if the top surface of the semiconductor chip (1) is divided into a large number of mats of substantially the same size along the partition line (5), and a plurality of electronic circuit blocks with different functions are housed in an integral number of mats, the electronic circuit blocks Each project can be designed in parallel, significantly shortening the design period.

Furthermore, since the electronic circuit block can be divided into a fixed number of elements and designed for each mat, parallel design for each mat can be performed.

Further, since circuit changes such as deletion, addition, and modification can be designed for each electronic circuit block or each block, only the change for each block or mat = 27- is sufficient, and there is no need to change the design of the entire IC.

Furthermore, mats can be made into cells as basic blocks, so
Once the design is complete, when changing the circuit afterwards, you only have to modify the mat to be changed, and the other mats can be used as they are, resulting in extremely high reliability.

Moreover, in a mat-divided semiconductor integrated circuit that facilitates this design, the side of the FM-IF block corresponding to the area where the FM front end block is formed, here the left side of mat E and mat E to mat By providing a suction electrode on the lower side of J, leakage current flowing from the mat on which the FM front end block is formed to between the mats is sucked out. Therefore, in the IC in this mat division, it is possible to integrate the FM-IF block and the FM front-end block into one chip.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a top view showing an embodiment of the semiconductor integrated circuit of the present invention, FIG. 2A is a top view showing a mat area of the semiconductor integrated circuit of the present invention, and FIG. 2A is a cross-sectional view taken along line AA' in FIG. 3A, FIG. 3 is a block diagram of an electronic circuit incorporated in the semiconductor integrated circuit of the present invention, FIG. 4A is a diagram illustrating an AM tuner block, and FIG. 4B is an FM tuner block diagram. Figure 4C is a diagram explaining the front end block and FM-IF block. Figure 4C is a diagram explaining the multiplex decoder block.
The figure is the electrode pattern diagram of Figure 1, Figure 6 is the dummy island pattern diagram of Figure 1, Figure 7A is a top view when capacitors are integrated on mat E, and Figure 7B is the same as Figure 7A. 8 is a top view of a conventional semiconductor integrated circuit, and FIG. 9 is a sectional view taken along line AA', and FIG. 9 is a sectional view taken between block b and block C in FIG. (1>...semiconductor chip, (2)...divided area,
(3)...first area, (4)...second area, (5)...division line, (37>, (38)
), (39), (40)...Third power line, (43), (44), (45), (
46)...Second ground line, (72),
(73), (74)...second power line,
(75), (76), (77)...Third ground line. Figure 4A Figure 4C

Claims (10)

[Claims] (1) A semiconductor integrated circuit in which an FM front-end block and an FM-IF block are formed on one semiconductor chip, and a semiconductor substrate is provided on the side of the FM-IF block corresponding to the FM front-end block side. A semiconductor integrated circuit characterized by being provided with a suction electrode that absorbs leakage current. (2) The semiconductor integrated circuit according to claim 1, wherein the extraction electrode is connected to a ground line or a ground pad. (3) The semiconductor integrated circuit according to claim 2, wherein the suction electrode is in contact with a separation region provided under the electrode over substantially the entire surface. (4) The semiconductor integrated circuit according to claim 3, wherein the suction electrode extends around the periphery of the semiconductor chip. (5) The semiconductor integrated circuit according to claim 3, wherein the capacitors included in the FM-IF block are integrated in a specific area of the area where the FM-IF block is formed, and a suction electrode is provided around the specific area. . (6) A semiconductor chip is formed by dividing a semiconductor chip into a plurality of regions of substantially the same size by arranging a plurality of division lines in the same direction, each of which is a set of power supply lines and ground lines extending adjacent to each other. A mat, and an electronic circuit constituted by a plurality of electronic circuit blocks having different functions that are incorporated in an integral number of the mat areas, and first and second electronic circuit blocks constituting the electronic circuit are configured as an FM front end. A semiconductor integrated circuit, which is a block and an FM-IF block, and is characterized in that a suction electrode is provided on the side of a second electronic circuit block corresponding to the first electronic circuit block side to absorb leakage current of the semiconductor substrate. . (7) The semiconductor integrated circuit according to claim 6, wherein the extraction electrode is connected to a ground line or a ground pad. (8) The semiconductor integrated circuit according to claim 7, wherein the suction electrode is in contact with a separation region provided under the electrode over substantially the entire surface. (9) The semiconductor integrated circuit according to claim 8, wherein the suction electrode extends around the periphery of the semiconductor chip. (10) The semiconductor integrated circuit according to claim 8, wherein the capacitors included in the FM-IF block are integrated on a specific mat forming the FM-IF block, and a suction electrode is provided around the mat.