JPH02237123A - Field-effect transistor - Google Patents

Abstract

PURPOSE:To be provided with a high gate breakdown strength irrespective of an alignment accuracy at a photolithographic operation and irrespective of a state on the surface of GaAs by a method wherein a Schottky electrode which is not connected electrically to the outside is bonded to the surface of a semiconductor between a gate electrode and a drain electrode. CONSTITUTION:A Schottky electrode 7 which is not connected electrically to the outside is formed in one part of the surface of a semiconductor substrate 1 between a gate electrode 4 and a drain electrode 6. Accordingly, a depletion layer by a Schottky barrier is produced directly under the electrode 7; the depletion layer is thicker than a surface depletion layer on the surface of GaAs; accordingly, a route of an electric current in an n-layer is pushed effectively to the side of the substrate 1; an electric field which has been concentrated in ends of the gate electrode and the drain electrode can be dispersed. Thereby, it is possible to enhance a gate breakdown strength.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to field effect transistors, and in particular to GaAs field effect transistors (hereinafter referred to as
This relates to the structure of a CaAsFET (abbreviated as CaAsFET).

[Conventional technology]

Figure 6 is a cross-sectional view of the main parts of a conventional C,aAsFET. In the figure, 1 is a semi-insulating GaAs substrate, 2 is an n
type conductive layer (hereinafter abbreviated as nFJ), 3a and 3b are n layer 2
It is an n+ layer with a lower resistance than that of the n+ layer.

Reference numeral 4 denotes a gate electrode formed on the n-layer 2, forming a Schottky junction with the n-layer 2. 5 is a source electrode forming an ohmic contact with the n'' layer 3a, and 6 is a drain electrode forming an ohmic contact with the n'' layer 3b.The gate electrode 4 is placed close to the source electrode 5 in the nN STJ region. It is formed.

The illustrated FET is a type of MESFET, in which electrons flowing from the source electrode 5 to the drain t-pole 6 through the n-layer 2 are formed by the width of a depletion layer created directly under the gate electrode by the voltage applied to the gate electrode 4. This is a transistor that is controlled by modulating the GaAs MESFETs using GaAs as a semiconductor material are already being put into practical use as active elements that operate at very high frequencies in the microwave region.

When G a As M E S F E T is used for high output applications, the most important characteristic is the reverse breakdown voltage (hereinafter abbreviated as gate breakdown voltage) between the gate electrode 4 and the drain electrode 6. Although it depends on the voltage, usually about 10 to 20V is required. It is known that this gate breakdown voltage increases as the distance between the gate electrode and the drain electrode increases. On the other hand, mutual conductance gm is an important performance of an FET, and this value shows a better value as the resistance R between the source and gate is smaller. Since R can be made smaller as the source-gate interval is made smaller, from this point of view it is required that the source-gate interval be made smaller. Based on the above two requirements, an FET (referred to as an offset gate FET) having an electrode arrangement as shown in FIG. 6 has been considered.

[Problem to be solved by the invention]

However, the conventional high gate breakdown voltage FET is configured as described above, and the gate-drain interval is usually determined by the positioning of the gate electrode to be formed. This positioning is performed by photolithography, but a high degree of alignment accuracy is required to stabilize the characteristics. In reality, there are variations in gate breakdown voltage due to alignment errors, and GaA
There are variations in gate breakdown voltage due to the influence of surface conditions, leading to a decrease in yield in the manufacture of high-performance, high-output FETs or integrated circuits using the same.

This invention was made to solve the above-mentioned problems, and aims to provide a field effect transistor having a high gate breakdown voltage without being affected by the alignment accuracy of photolithography technology or the condition of the GaAs surface. purpose.

[Means to solve the problem]

A field effect transistor according to the present invention is provided with a Schottky electrode that is not electrically connected to the outside on a part of the surface of a semiconductor substrate between a gate electrode and a drain electrode.

[Effect]

In this invention, since a Schottky electrode is formed on the surface of the n-layer between the gate and drain, a depletion layer due to a Schottky barrier is generated directly under the electrode, and the thickness of the depletion layer is larger than that of the surface depletion layer on the GaAs surface. Therefore, the current path in the n-layer is effectively pushed toward the substrate side,
The electric field concentrated at the ends of the gate electrode and the drain electrode can be dispersed, thereby making it possible to improve the gate breakdown voltage.

〔Example〕

Hereinafter, one embodiment of the present invention will be explained with reference to the drawings.

FIG. 1 is a diagram showing a field effect transistor according to a first embodiment of the present invention, in which 1 is a semi-insulating GaA transistor.
s substrate, 2 is nJi, 3a and 3b are source and drain n'' layers, 4 is a gate electrode, 4a is its pad part,
5 is a source electrode, 6 is a drain electrode, and 7 is an electrode that makes Schottky contact with the surface of the n-layer between the gate and the drain.

Moreover, FIG. 2 is a perspective view of FIG. 1. As shown in the figure, the chip electrode 7 is not connected to an external circuit, and a pad portion like the butt portion 4a of the gate electrode 4 is unnecessary. There is already something called a dual gate FE'I' which connects the Schottky electrode 7 to an external circuit and performs the same operation as the gate electrode 4, but the structure of the present invention does not connect to an external circuit. It differs from a dual-gate structure in that it has a Schottky electrode in a so-called floating state. Next, the method for manufacturing the field effect transistor of the present invention will be explained. FIGS. 3(a) to 3(d) are sectional views of main parts of the main manufacturing process. In the figures, the same reference numerals as in FIG. 1 indicate the same parts, and 8a, 8b, and 8c are photoresist patterns.

First, an n layer 2 exhibiting n-type conductivity is formed on a semi-insulating GaAs substrate 1. In order to form the n-layer only in desired regions, known ion implantation techniques, epitaxial growth techniques, mesa etching techniques, etc. are used (FIG. 2(a)). Next, a gate electrode 4 and a Schottky electrode 7 that form a Schottky junction are formed on the surface of the n-layer 2 (FIG. 2(b)).

Typically, both electrodes can be formed from the same material. In this example, since a high temperature treatment process is performed later, a high melting point material widely used as a heat-resistant Schottky electrode material, such as WSi (tagsten silicide), was used. The electrode pattern can be formed by sputtering and RIE (reactive ion etching). Both t-poles were formed to have the same length (width in the figure) of 1 μm. Next, as shown in the same figure (C), a photoresist pattern 8a is formed.
8c, Si ions are introduced by ion implantation, and appropriate heat treatment is performed to form low resistance n' layers 3a and 3b. Finally, source and drain electrodes 5, 6
is formed, and the main part of the FET is completed ((d) in the same figure).

In this embodiment, since the Schottky electrode 7 is formed between the gate electrode 4 and the drain electrode 6, a depletion layer due to a Schottky barrier is generated directly under the electrode 7.
Effectively n[1 out of 2! The flow path is pushed toward the substrate 1 side, and the electric field concentrated at the ends of the gate electrode and the drain electrode can be dispersed, and the gate withstand voltage can be improved. In the first embodiment described above, the lengths of the gate electrode 4 and the digital electrode 7 (referring to the length in the lateral direction of each electrode in FIG. 1) are equal. In this case, if the depletion layer thickness due to the Schottky electrode 7 occupies a large proportion of the thickness of the n-layer 2, the current value that can flow between the drain and source becomes small, and depending on the application, the current value may exceed the required value. There may be cases where the desired performance cannot be obtained. In order to deal with cases such as when a large current is required, the n
A structure in which the current that can be passed through the lower part of the Schottky electrode 7 is made thicker is shown below without changing the jl concentration or thickness.

That is, FIG. 4 shows a field effect transistor according to the second embodiment of the present invention, which is characterized in that the length of the Schottky electrode 7 is shorter than the gate electrode 4, and the other features are the same as in the first embodiment.
It has a structure similar to that of the embodiment. Schottky electrode 7
The thickness of the depletion layer generated by this is the same as in the first embodiment, but its width is reduced by the length of the electrode. As a result, the current that can flow between the source and drain can be increased without causing a decrease in gate breakdown voltage due to the effect of alleviating electric field concentration.

FIG. 5 shows a field effect transistor according to a third embodiment of the present invention, and in the first and second embodiments, the n'' layers 3a and 3b are used as gate electrodes for the purpose of reducing parasitic resistance. 4, this can also be applied to an FET having no n'' layer as in this embodiment. In this case, since high temperature treatment is not required after gate formation, there is no need to use a high melting point material such as WSi as the material for the gate electrode 7, and the structure includes a low melting point material such as Au or 82. It is possible to do so.

(Effects of the Invention) As described above, according to the present invention, since a floating Schottky electrode is formed between the gate electrode and the drain electrode, the gate breakdown voltage of the FET can be improved.
In addition, since the effect is not easily affected by the surface condition of the element, it is possible to stably manufacture high-output field effect transistors.

[Brief explanation of drawings]

FIG. 1 is a sectional view of essential parts of a field effect transistor according to a first embodiment of the present invention, FIG. 2 is a perspective view of the field effect transistor of FIG. 1, and FIGS. FIG. 1 is a cross-sectional view of main parts showing the main manufacturing process of the field effect transistor, FIG. 4 is a cross-sectional view of main parts showing a field effect transistor according to a second embodiment of the present invention, and FIG. A sectional view of a main part showing a field effect transistor according to an embodiment of
FIG. 6 is a sectional view of a main part of a conventional field effect transistor. In the figure, 1 is a semi-insulating GaAs substrate, 2 is an n-type conductive layer, 3a and 3b are n'' layers, 4 is a gate electrode, 4a is a pad part of the gate electrode, 5 is a source electrode, 6 is a drain electrode, and 7 8 is a Schottky electrode, and 8a, 8b, and 8c are photoresist patterns. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] (1) In a high-output field effect transistor in which a metal gate electrode is formed by a Schottky junction on the semiconductor surface and a source electrode and a drain electrode are arranged with the gate electrode in between, the gate electrode and the drain electrode are A field effect transistor characterized in that a Schottky electrode, which is not electrically connected to the outside, is bonded to the surface of the semiconductor in between.