JPH02249242A - Alignment of chip bonding - Google Patents

Alignment of chip bonding

Info

Publication number
JPH02249242A
JPH02249242A JP63260449A JP26044988A JPH02249242A JP H02249242 A JPH02249242 A JP H02249242A JP 63260449 A JP63260449 A JP 63260449A JP 26044988 A JP26044988 A JP 26044988A JP H02249242 A JPH02249242 A JP H02249242A
Authority
JP
Japan
Prior art keywords
chip
substrate
board
positioning table
bonding tool
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP63260449A
Other languages
Japanese (ja)
Other versions
JPH039621B2 (en
Inventor
Noboru Fujino
昇 藤野
Seiichi Chiba
誠一 千葉
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinkawa Ltd
Original Assignee
Shinkawa Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinkawa Ltd filed Critical Shinkawa Ltd
Priority to JP63260449A priority Critical patent/JPH02249242A/en
Publication of JPH02249242A publication Critical patent/JPH02249242A/en
Publication of JPH039621B2 publication Critical patent/JPH039621B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/071Connecting or disconnecting
    • H10W72/0711Apparatus therefor
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/071Connecting or disconnecting
    • H10W72/0711Apparatus therefor
    • H10W72/07178Means for aligning
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/071Connecting or disconnecting
    • H10W72/072Connecting or disconnecting of bump connectors
    • H10W72/07251Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/20Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps

Landscapes

  • Wire Bonding (AREA)
  • Die Bonding (AREA)

Abstract

PURPOSE:To facilitate accurate alignment whether a substrate is transparent or not by a method wherein the image of the substrate is picked up by a substrate detecting camera and the image of a chip is picked up by a chip detecting camera and the two images are synthesized into one image which is displayed by one monitor to align the chip with the substrate. CONSTITUTION:A substrate 1 is placed on a substrate positioning table 20 and a chip 2 is attracted by a bonding tool 23. The image of the substrate 1 on the substrate positioning table 20 is picked up by a substrate detecting camera 21 provided above the substrate positioning table 20 and the image of the chip 2 attracted by the bonding tool 23 is picked up by a chip detecting camera 22 provided away from the substrate positioning table 20. The two images picked up the two cameras 21 and 22 are synthesized into one image which is displayed by one monitor 33 to align the chip 2 with the substrate 1. For instance, the substrate detecting camera 21 is fixed to a point B directly above the reference point A of the substrate positioning table 20 and the chip detecting camera 22 is provided at a point C away from the reference point A by a distance X1 and Y1 so as to be able to rotate and to move along the X and Y directions.

Description

【発明の詳細な説明】 [産業上の利用分野1 本発明は半導体装置を製造するために基板のパッド又は
リード(以下リードの場合について述べる)に直接チッ
プのバンプを重ね合せてポンディングするフェースダウ
ン方式のチップボンディングの位置合せ方法に関する。
Detailed Description of the Invention [Industrial Application Field 1] The present invention is a face bonding method in which bumps of a chip are directly stacked on pads or leads (the case of leads will be described below) of a substrate in order to manufacture semiconductor devices. The present invention relates to an alignment method for down-type chip bonding.

[従来の技術ゴ 従来、かかるチップボンディングにおいて基板のリード
とチップのバンプとの位置合せは、第5図又は第6図に
示す方法で行われている。
[Prior Art] Conventionally, in such chip bonding, the alignment of the leads of the substrate and the bumps of the chip is performed by the method shown in FIG. 5 or 6.

第5図の方法は、図示しないポンディングステーション
に位置決め保持された基板lの上方にチップ2がボンデ
ィングツール3に吸着保持されて位置し、基板1の下方
に配設されたカメラ4により基板lとチップ2を同一画
面上に写し、基板lのリード1aとチップ2のバンプ2
aが重なるように位置合せする0図中、5はハーフミラ
−16はランプを示す。
In the method shown in FIG. 5, a chip 2 is held by a bonding tool 3 by suction above a substrate l which is positioned and held in a bonding station (not shown), and a camera 4 disposed below the substrate 1 is used to detect the substrate l. and chip 2 on the same screen, lead 1a of board l and bump 2 of chip 2.
In the figure, 5 indicates a half mirror and 16 indicates a lamp.

第6図の方法は、カメラ10及びハーフミラ−11を基
板lの上方に配設し、ランプ12による基板1の反射光
及びランプ13によるチップ2の反射光をハーフミラ−
11を用いて基板1とチップ2をカメラ10の同一画面
上に写し、基板1のリード1aとチップ2のバンプ2a
が重なるように位置合せする。
In the method shown in FIG. 6, a camera 10 and a half mirror 11 are disposed above the substrate 1, and the light reflected from the substrate 1 by the lamp 12 and the light reflected from the chip 2 by the lamp 13 are transferred to the half mirror.
11 to capture the board 1 and the chip 2 on the same screen of the camera 10, and the leads 1a of the board 1 and the bumps 2a of the chip 2.
Align so that they overlap.

[発明が解決しようとする課題] 第5図の方法は、基板lを通してチップ2を写し出すの
で、基板lが透明でないと適応できない。
[Problems to be Solved by the Invention] Since the method shown in FIG. 5 projects the chip 2 through the substrate l, it cannot be applied unless the substrate l is transparent.

第6図の方法は、反射光によるので、基板1が不透明で
あっても検知できる。しかし、この方法はハーフミラ−
11の使用数を最小限にし、構造を簡単にするには図示
のように基板lの中心とチップ2の中心が垂直線上に、
また基板l、チップ2、ハーフミラ−11が水平に、更
に全ての入射角及び反射角が同一の角度θ1にそれぞれ
がなるようにしなければならない、このため、基板1を
載置する台、ボンディングツール3、カメラ10、ハー
フミラ−11の配置が制限され、設置が困難になる場合
が生じる。また角度θ、がどれか1つでもずれると位置
ずれが生じる欠点を有する。
Since the method shown in FIG. 6 uses reflected light, it can be detected even if the substrate 1 is opaque. However, this method
In order to minimize the number of chips 11 used and simplify the structure, the center of the substrate 1 and the center of the chip 2 should be on a perpendicular line as shown in the figure.
In addition, the substrate 1, the chip 2, and the half mirror 11 must be placed horizontally, and all incident angles and reflection angles must be at the same angle θ1.For this purpose, a table on which the substrate 1 is placed, a bonding tool, etc. 3. The arrangement of the camera 10 and half mirror 11 may be restricted, making installation difficult. Further, there is a drawback that if even one of the angles θ is shifted, a positional shift occurs.

本発明の目的は、基板が透明、不透明にかかわらず適応
可能で、より正確に位置合せすることができるチップボ
ンディングの位置合せ方法を提供することにある。
An object of the present invention is to provide a chip bonding alignment method that is applicable regardless of whether the substrate is transparent or opaque, and allows for more accurate alignment.

[課題を解決するための手段] 上記目的は、基板を基板位置決め台に載置し、チップを
ボンディングツールで吸着させ、前記基板位置決め台の
上方に配設された基板検知用カメラで基板位置決め台上
の基板を写し、前記基板位置決め台から離れた場所に配
設されたチップ検知用カメラで前記ボンディングツール
に吸着されたチップを写し、前記2台のカメラで取り出
した2つの映像を合成回路を用いて1つのモニタに合成
して写し出し、基板とチップとを位置合せすることによ
り達成される。
[Means for Solving the Problems] The above object is to place a board on a board positioning table, adsorb a chip with a bonding tool, and use a board detection camera disposed above the board positioning table to position the board on the board positioning table. The above board is photographed, the chip adsorbed to the bonding tool is photographed using a chip detection camera placed at a location away from the board positioning table, and the two images taken by the two cameras are combined into a circuit. This is accomplished by combining and projecting the images on one monitor and aligning the substrate and chip.

[作用1 基板とチップとを離れた場所でそれぞれに対応して設け
られた2台のカメラで2つの映像として取り出し、合成
回路を使って1つのモニタに合成して写し出し、基板と
チップとを離れた場所で位置合せする。従って、基板が
透明、不透明にかかわらず適応できると共に、位置合せ
が簡単にかつ正確に行える。またカメラを任意の位置に
設置することができ、またカメラの角度の設定が容易に
でき、位置ずれが生じにくくなる。
[Effect 1: The board and chip are captured as two images using two cameras installed at separate locations, and the composite circuit is used to combine and display the images on a single monitor. Align at a remote location. Therefore, it can be applied regardless of whether the substrate is transparent or opaque, and alignment can be performed easily and accurately. Furthermore, the camera can be installed at any position, and the angle of the camera can be easily set, making it difficult for positional deviation to occur.

[実施例] 以下、本発明の一実施例を第1図乃至第4図により説明
する。第1図に示すように、基板位置決め台20に載置
された基板lを検知する基板検知用カメラ21と、ボン
ディングツール23に吸着保持されたチップ2を検知す
るチップ検知用カメラ22とが配設されている。基板検
知用カメラ21は基板位置決め台20の基準点A(例え
ばポンディング位置)の真上のB点に固定されている。
[Example] An example of the present invention will be described below with reference to FIGS. 1 to 4. As shown in FIG. 1, a substrate detection camera 21 that detects the substrate l placed on the substrate positioning table 20 and a chip detection camera 22 that detects the chip 2 held by the bonding tool 23 are arranged. It is set up. The substrate detection camera 21 is fixed at a point B on the substrate positioning table 20 directly above the reference point A (for example, the bonding position).

チップ検知用カメラ22は回転及びXY力方向移動可能
で、基準点Aより離れた0点に配設されている。ボンデ
ィングツール23は上下(Z)とXY力方向移動及び回
転可能に設けられており、0点の真上のD点及びA点の
真上のE点に位置することができる。また基板位置決め
台20の前後には基板lを基板位置決め台20に送り込
み及び送り出す基板フィーダー24が配設されている。
The chip detection camera 22 is rotatable and movable in the XY force directions, and is disposed at a zero point away from the reference point A. The bonding tool 23 is provided so as to be movable and rotatable in the vertical (Z) and XY force directions, and can be positioned at point D directly above point 0 and point E directly above point A. Further, a substrate feeder 24 is provided before and after the substrate positioning table 20 for feeding and feeding the substrate l to the substrate positioning table 20.

前記2台のカメラ21.22は、第2図に示すように、
タイミング回路30により偏向回路31に設定された立
上り、立下り時間の信号が入力されており、カメラ21
.22が映像ビームを信号に変換し、合成回路32によ
り2台のカメラ21,22からの信号を合成、増幅し、
モニタ33に入力して合成画像を写すようになっている
The two cameras 21 and 22, as shown in FIG.
The timing circuit 30 inputs rise and fall time signals set to the deflection circuit 31, and the camera 21
.. 22 converts the video beam into a signal, and a synthesis circuit 32 synthesizes and amplifies the signals from the two cameras 21 and 22.
The composite image is displayed by inputting it to a monitor 33.

次に本発明の方法について説明する。まず、第3図に示
すように基板位置決め台20のA点上にマーク40又は
それに代るものが付された2枚の透明板41.42をそ
のマーク40を一致させて収納した治具43を固定する
。これを基板検知用カメラ21で写す、当然、この状態
においては2枚の透明板41.42のマーク40は重な
ってモニタ33(第2図参照)に移る。
Next, the method of the present invention will be explained. First, as shown in FIG. 3, a jig 43 stores two transparent plates 41 and 42 with a mark 40 or an alternative thereon on the point A of the substrate positioning table 20 with the marks 40 aligned. to be fixed. This is photographed by the substrate detection camera 21. Naturally, in this state, the marks 40 on the two transparent plates 41 and 42 overlap and are transferred to the monitor 33 (see FIG. 2).

次にボンディングツール23を電気マニピュレータを用
いてXY力方向移動させてA点の真上のE点に位置させ
る。続いてボンディングツール23を下降させて最上の
透明板41を吸着させ、再びE点に上昇又は上昇しなか
らXY力方向移動させてD点に位置させる。この時のボ
ンディングツール23のxY力方向距離xt、ytをコ
ンピュータ等に記憶させておく、ボンディングツール2
3がD点に位置すると、ボンディングツール23に吸着
されている透明板41をチップ検知用カメラ22で写す
、そこで、基板検知用カメラ21で写している残った透
明板4zとチップ検知用カメラ22で写している透明板
41の2つの映像を第2図に示す合成回路32を通して
合成画像とし、1台のモニタ33上に写し、透明板41
.42の合せマーク40が一致するようにチップ検知用
カメラ22の位置及び倍率を調整する。基板検知用カメ
ラ21の位置及び倍率はボンディングツール23で透明
板41を吸着する前に設定しておく。
Next, the bonding tool 23 is moved in the XY force direction using an electric manipulator to position it at point E directly above point A. Subsequently, the bonding tool 23 is lowered to attract the uppermost transparent plate 41, and again rises or rises to point E, and then moves in the XY force direction to position it at point D. The bonding tool 2 stores the xY force direction distances xt and yt of the bonding tool 23 at this time in a computer or the like.
3 is located at point D, the chip detection camera 22 photographs the transparent plate 41 that is adsorbed to the bonding tool 23, and the remaining transparent plate 4z photographed by the board detection camera 21 and the chip detection camera 22. The two images of the transparent plate 41 shown in the image are made into a composite image through the combining circuit 32 shown in FIG.
.. The position and magnification of the chip detection camera 22 are adjusted so that the alignment marks 40 of 42 coincide with each other. The position and magnification of the substrate detection camera 21 are set before the bonding tool 23 adsorbs the transparent plate 41.

これにより、2台のカメラの倍率及び位置の調整が完了
する。そこで、透明板41.42及び治具43を取除く
This completes the adjustment of the magnification and position of the two cameras. Therefore, the transparent plates 41 and 42 and the jig 43 are removed.

次に第1図に示すように、実際の試料である基板1を基
板位置決め台20のA点に位置決め載置し、チップ2を
ボンディングツール3に吸着させ、基板検知用カメラ2
1をB点に、ボンディングツール23をD点にそれぞれ
位置させる。そして、基板1を基板検知用カメラ21で
、チップ2をチップ検知用カメラ22でそれぞれ写すと
、第2図に示す合成回路32を通してモニタ33上に第
4図(a)に示すように合成画像として写し出される0
次にチップ2、即ちボンディングツール23を回転及び
XY力方向移動させ、又は基板位置決め台20を回転及
びXY力方向動作させ、同図(C)に示すように基板1
のリードIaとチップ2のバンプ2aとを合せる。この
位置合せ方法については種々の方法が考えられるが、そ
の方法については後述する。
Next, as shown in FIG. 1, the substrate 1, which is an actual sample, is positioned and placed on point A of the substrate positioning table 20, the chip 2 is attracted to the bonding tool 3, and the substrate detection camera 2
1 at point B and the bonding tool 23 at point D, respectively. Then, when the board 1 is photographed by the board detection camera 21 and the chip 2 is photographed by the chip detection camera 22, a composite image is displayed on the monitor 33 through the composition circuit 32 shown in FIG. 2 as shown in FIG. 4(a). 0 projected as
Next, the chip 2, that is, the bonding tool 23 is rotated and moved in the XY force direction, or the substrate positioning table 20 is rotated and moved in the XY force direction, so that the substrate
Align the leads Ia and the bumps 2a of the chip 2. Various methods can be considered for this positioning method, which will be described later.

次にボンディングツール23を第1図の説明において定
めたXl、Ylの距離移動させて基板1の真上のE点に
位置させ、続いてボンディングツール23を下降させて
基板lにチップ2を押付けると、基板lのリードlaに
チップ2のバンプ2aが重ね合せられて正確にポンディ
ングされる。
Next, the bonding tool 23 is moved the distance Xl, Yl determined in the explanation of FIG. When attached, the bumps 2a of the chip 2 are superimposed on the leads la of the substrate l, and are bonded accurately.

以降、第1図において説明した動作を手動又は自動で行
い、順次ポンディングが自動的に行われる。
Thereafter, the operations described in FIG. 1 are performed manually or automatically, and bonding is performed automatically in sequence.

次に第4図(a)の状態より同図(C)に示すように基
板1及びチップ2を位置合せする方法を2つ説明する。
Next, two methods for aligning the substrate 1 and the chip 2 from the state shown in FIG. 4(a) as shown in FIG. 4(C) will be described.

第4図Ca’)において、実線で示すx、yは基準のク
ロスライン、−点鎖線で示すx’、y’は基板1の基準
ライン、点線で示すx”、y’“はチップ2の基準ライ
ンをそれぞれ示す、またθ′は基準ラインx、yから基
準ラインx’、y’の傾き、即ち基板1の傾き角度、θ
°°は基準ラインx、yから基準ラインX”、y”の傾
き、即ちチップ2の傾き角度をそれぞれ示す、そこで、
0゛、θ°°を求め、チップ2又は基板1をθ=θ゛′
−θ°だけ回転させると、同図(b)(図は基板lを回
転させた状態)に示すように基板1とチップ2が平行に
なる0次にチップ2をX方向にΔx、Y方向にΔy移動
(平行移動)させると、チップ2のa点はり−ド1aの
b点に合い、同図(C)に示すようにリードlaとバン
プ2aが重なる。実際はθ方向及びxY力方向同時に動
かし。
In Fig. 4 Ca'), x and y indicated by solid lines are reference cross lines, The reference lines are respectively shown, and θ' is the inclination of the reference lines x', y' from the reference lines x, y, that is, the inclination angle of the substrate 1, θ'
°° indicates the inclination of the reference lines X", y" from the reference lines x, y, that is, the inclination angle of the chip 2, respectively;
0゛, θ°°, and chip 2 or substrate 1 as θ=θ゛'
When rotated by -θ°, substrate 1 and chip 2 become parallel as shown in Figure (b) (the figure shows the state in which substrate l has been rotated). When the chip 2 is moved by Δy (parallel movement), the point a of the chip 2 aligns with the point b of the lead 1a, and the lead la and the bump 2a overlap as shown in FIG. 2C. In reality, it moves simultaneously in the θ direction and the xY force direction.

第4図(a)の状態から1度に同図(C)の状態になる
The state shown in FIG. 4(a) changes to the state shown in FIG. 4(C) all at once.

他の方法としては、第4図(a)に示すようにチツブ2
の任意の2点a1、a2及び基板1の任意の2点b1、
b2を予め決めておく、まず、チップ2の傾き角度αを
求める。予め決めたa、、a2の基準ラインxy方向の
ずれをΔx1、−「Δy2 基板lの傾き角βを求めると、β=j anτことなる
。従って、基板lとチップ2どのずれ角度θはθ=α−
βで求まる。ここで、θ〉0は図から見ると右回り、θ
く0は図から見ると左回りである。そこで、基板lをθ
回転させると、同図(b)に示すように基板1とチップ
2が平行になる0次に予め定めたチップ2の1点alと
基板1の1点す、とのずれΔX、Δyを検出し、チップ
2をX軸方向にΔx、y軸方向にΔy移動させると、同
図(C)のようにリード1aとバンブ2aが重なる。こ
のように、予め基板1及びチップ2にそれぞれ任意の2
点を決め、どの点とどの点が対応するかを決めておけば
、自動検出して自動ボンディングが行える。
Another method is to use the tip 2 as shown in Figure 4(a).
any two points a1, a2 on the substrate 1, and any two points b1 on the substrate 1,
b2 is determined in advance. First, the inclination angle α of the chip 2 is determined. The deviation in the xy direction of the reference line of the predetermined a, a2 is Δx1, - Δy2. If the inclination angle β of the substrate l is determined, β=j anτ. Therefore, the deviation angle θ between the substrate l and the chip 2 is θ =α−
It is determined by β. Here, θ〉0 is clockwise as seen from the figure, θ
0 means counterclockwise rotation as seen from the diagram. Therefore, the substrate l is θ
When rotated, the substrate 1 and the chip 2 become parallel as shown in the same figure (b).The deviation ΔX, Δy between the predetermined point al of the chip 2 and the point S of the substrate 1, which are predetermined in the 0th order, is detected. However, when the chip 2 is moved by Δx in the X-axis direction and Δy in the y-axis direction, the leads 1a and the bumps 2a overlap as shown in FIG. In this way, any arbitrary two
By determining points and determining which points correspond to which points, automatic detection and automatic bonding can be performed.

なお、第3図において説明した2台のカメラ21.22
の倍率及び位置調整は初めに一度行うのみでよく、以降
の位置合せ及びボンディング時には必要としない、また
倍率調整において第3図に示すように透明板41.42
に十字マーク40を付したが、特にこれに限定されるも
のではなく、三角、四角、丸のマークを付してもよく、
またマーク40は付さなく、透明板41.42の大きさ
を同じにし、外形で合せるようにしてもよい、また実施
例は、ボンディングツール23を基板位置決め台20の
位置よりチップ検知用カメラ22の上方まで移動させた
XY力方向位置を算出したが、既に基板位置決め台20
の位置からチップ検知用カメラ22の上方までの距離が
予め判明している時は、この距離を改めて算出させる必
要がないことはいうまでもない。
Note that the two cameras 21 and 22 explained in FIG.
It is only necessary to adjust the magnification and position once at the beginning, and it is not necessary during subsequent alignment and bonding.
Although a cross mark 40 is attached to the mark, the present invention is not limited to this, and triangle, square, or circle marks may also be attached.
Alternatively, the marks 40 may not be attached, and the transparent plates 41 and 42 may have the same size so that their outer shapes match. Although the position in the XY force direction was calculated when the board was moved upward, the position of the board positioning table 20 was already
It goes without saying that when the distance from the position to above the chip detection camera 22 is known in advance, there is no need to calculate this distance anew.

[発明の効果] 以上の説明から明らかなように、本発明になるチップボ
ンディングの位置合せ方法によれば、基板とチップとを
離れた場所でそれぞれに対応して設けられた2台のカメ
ラで2つの映像として取り出し1合成回路を使って1つ
のモニタに合成して写し出し、基板とチップとを離れた
場所で位置合せするので、基板が透明、不透明にかかわ
らず適応できると共に、位置合せが簡単にかつ正確に行
える。またカメラを任意の位置に設置することができ、
またカメラの角度の設定が容易にでき、従来技術におけ
るような位置ずれが生じにくくなる。
[Effects of the Invention] As is clear from the above explanation, according to the chip bonding alignment method of the present invention, two cameras installed correspondingly to the substrate and the chip can be used at separate locations. Since the two images are taken out and combined on one monitor using a compositing circuit, and the board and chip are aligned at a separate location, it can be applied regardless of whether the board is transparent or opaque, and alignment is easy. Can be performed quickly and accurately. Also, the camera can be installed in any position,
Furthermore, the angle of the camera can be easily set, and positional deviations that occur in the prior art are less likely to occur.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例を示し、(a)は正面説明図
、(b)は斜視説明図、第2図は回路図、第3図はカメ
ラの倍率調整方法を示し、(a)は正面説明図、(b)
は斜視説明図、第4図(a)(b)(c)はモニタ上に
写し出された基板1とチップ2との位置調整を示す説明
図、第5図は透明基板の場合における従来の方法を示す
説明図、第6図は不透明基板の場合における従来の方法
を示す説明図である。 1:基板、  2:チップ、 20:基板位置決め台、
  21:基板検知用カメラ、  22:チップ検知用
カメラ、   23:ボンディングツール、   32
:合成回路、   33:モニタ、40:マーク、  
 41.42:透明板。 (G) 22:チップ検知用カメラ 23:ボンディングツール (a) 第 図 2:チップ zO:基板位置決め合 21:基板検知用カメラ 22:チップ検知用カメラ 23:ボンディングツール 第 図 (b) 20:基板位置決め台 2L:基板検知用カメラ 22:チップ検知用カメラ 23:ボンディングツール 40:マーク 41.42:透明板
Fig. 1 shows an embodiment of the present invention, (a) is a front view, (b) is a perspective view, Fig. 2 is a circuit diagram, and Fig. 3 is a method for adjusting the magnification of the camera. ) is a front explanatory view, (b)
4(a), 4(b), and 4(c) are illustrations showing the position adjustment of the substrate 1 and chip 2 projected on the monitor, and FIG. 5 is a conventional method in the case of a transparent substrate. FIG. 6 is an explanatory diagram showing a conventional method in the case of an opaque substrate. 1: Board, 2: Chip, 20: Board positioning stand,
21: Board detection camera, 22: Chip detection camera, 23: Bonding tool, 32
: synthesis circuit, 33: monitor, 40: mark,
41.42: Transparent plate. (G) 22: Chip detection camera 23: Bonding tool (a) Figure 2: Chip zO: Board positioning 21: Board detection camera 22: Chip detection camera 23: Bonding tool Figure (b) 20: Board Positioning table 2L: Board detection camera 22: Chip detection camera 23: Bonding tool 40: Marks 41.42: Transparent plate

Claims (2)

【特許請求の範囲】[Claims] (1)基板を基板位置決め台に載置し、チップをボンデ
ィングツールで吸着させ、前記基板位置決め台の上方に
配設された基板検知用カメラで基板位置決め台上の基板
を写し、前記基板位置決め台から離れた場所に配設され
たチップ検知用カメラで前記ボンディングツールに吸着
されたチップを写し、前記2台のカメラで取り出した2
つの映像を合成回路を用いて1つのモニタに合成して写
し出し、基板とチップとを位置合せすることを特徴とす
るチップボンディングの位置合せ方法。
(1) Place the board on the board positioning table, adsorb the chip with a bonding tool, photograph the board on the board positioning table with a board detection camera disposed above the board positioning table, and take a picture of the board on the board positioning table. A chip detection camera placed far away from the bonding tool captures the chip adsorbed to the bonding tool, and the two cameras take out the chip.
A chip bonding alignment method characterized in that two images are synthesized and displayed on one monitor using a synthesis circuit, and a substrate and a chip are aligned.
(2)マーク入り又は同じ大きさの2個の透明板の一方
を基板位置決め台に載置し、他方をボンディングツール
に吸着させ、基板位置決め台の上方に配設された基板検
知用カメラで前記基板位置決め台上の透明板を写し、前
記基板位置決め台から離れた場所に配設されたチップ検
知用カメラで前記ボンディングツールに吸着された透明
板を写し、前記2台のカメラで取り出した2つの映像を
合成回路を用いて1つのモニタに合成して写し、前記2
台のカメラの倍率及び位置を調整し、次に基板を基板位
置決め台に載置し、チップを前記ボンディングツールに
吸着させ、基板及びチップを前記2台のカメラで2つの
映像として取り出し、前記合成回路を用いて前記1つの
モニタに合成して写し出し、基板とチップとを位置合せ
することを特徴とするチップボンディングの位置合せ方
法。
(2) Place one of the two transparent plates with marks or of the same size on the substrate positioning table, attach the other to the bonding tool, and use the board detection camera installed above the substrate positioning table to The transparent plate on the substrate positioning table was photographed, the transparent plate adsorbed to the bonding tool was photographed using a chip detection camera placed at a location away from the substrate positioning table, and the two cameras taken out by the two cameras were photographed. The images are synthesized and displayed on one monitor using a synthesis circuit, and
Adjust the magnification and position of the camera on the stand, then place the board on the board positioning stand, adsorb the chip to the bonding tool, take out the board and chip as two images with the two cameras, and combine the A chip bonding alignment method characterized in that the substrate and the chip are aligned by combining and projecting the images on the one monitor using a circuit.
JP63260449A 1988-10-18 1988-10-18 Alignment of chip bonding Granted JPH02249242A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63260449A JPH02249242A (en) 1988-10-18 1988-10-18 Alignment of chip bonding

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63260449A JPH02249242A (en) 1988-10-18 1988-10-18 Alignment of chip bonding

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP56031619A Division JPS57147245A (en) 1981-03-05 1981-03-05 Positioning method and device for chip bonding

Publications (2)

Publication Number Publication Date
JPH02249242A true JPH02249242A (en) 1990-10-05
JPH039621B2 JPH039621B2 (en) 1991-02-08

Family

ID=17348093

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63260449A Granted JPH02249242A (en) 1988-10-18 1988-10-18 Alignment of chip bonding

Country Status (1)

Country Link
JP (1) JPH02249242A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH077028A (en) * 1993-06-16 1995-01-10 Shibuya Kogyo Co Ltd Semiconductor alignment method
JP2007173801A (en) * 2005-12-22 2007-07-05 Unaxis Internatl Trading Ltd Attaching the flip chip to the substrate

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH077028A (en) * 1993-06-16 1995-01-10 Shibuya Kogyo Co Ltd Semiconductor alignment method
JP2007173801A (en) * 2005-12-22 2007-07-05 Unaxis Internatl Trading Ltd Attaching the flip chip to the substrate

Also Published As

Publication number Publication date
JPH039621B2 (en) 1991-02-08

Similar Documents

Publication Publication Date Title
KR20210004872A (en) High-precision bond head positioning method and apparatus
TWI328840B (en)
CN102569105B (en) Wedge bonding method including remote image recognition system
JPH02249242A (en) Alignment of chip bonding
TWI544567B (en) Apparatus and method for using an imaging device to adjust a processing device of a semiconductor element
JPH0131296B2 (en)
JP2675307B2 (en) Preliner equipment
JP2003062912A (en) Film bonding equipment
JP3746238B2 (en) Semiconductor device manufacturing method and flip chip bonding apparatus
TWI492317B (en) The method of detecting the relative position of the grain adapter and the bonding tool and the semiconductor grain
JP2635755B2 (en) Electronic component positioning device
TW477021B (en) Method of precisely accessing and placing chip to align the substrate during flip chip bonding process
JPH04199525A (en) Flip chip bonder device and alignment thereof
JPH0613962B2 (en) IC wafer automatic positioning device
JPH0435846A (en) Positioning of semiconductor wafer
JPS5972145A (en) Device and method for flip chip bonding
US6381359B1 (en) Bonding apparatus
JPH0139216B2 (en)
KR102000870B1 (en) Apparatus for Bonding Flexible Part Including Inclined Leads
JPH01103292A (en) Camera fitting system to robot
JP2620568B2 (en) Component position / posture inspection device
JPH036842A (en) Detection of position of lead and bump in tape bonding
JPH07273148A (en) Positioning method when mounting electronic components on a circuit board
JPH09120986A (en) Pre-alignment method and pre-alignment apparatus
JPS6158245A (en) Ic chip positioning device