JPH039621B2 - - Google Patents

Info

Publication number
JPH039621B2
JPH039621B2 JP63260449A JP26044988A JPH039621B2 JP H039621 B2 JPH039621 B2 JP H039621B2 JP 63260449 A JP63260449 A JP 63260449A JP 26044988 A JP26044988 A JP 26044988A JP H039621 B2 JPH039621 B2 JP H039621B2
Authority
JP
Japan
Prior art keywords
chip
substrate
positioning table
board
bonding tool
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP63260449A
Other languages
Japanese (ja)
Other versions
JPH02249242A (en
Inventor
Noboru Fujino
Seiichi Chiba
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinkawa Ltd
Original Assignee
Shinkawa Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinkawa Ltd filed Critical Shinkawa Ltd
Priority to JP63260449A priority Critical patent/JPH02249242A/en
Publication of JPH02249242A publication Critical patent/JPH02249242A/en
Publication of JPH039621B2 publication Critical patent/JPH039621B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/071Connecting or disconnecting
    • H10W72/0711Apparatus therefor
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/071Connecting or disconnecting
    • H10W72/0711Apparatus therefor
    • H10W72/07178Means for aligning
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/071Connecting or disconnecting
    • H10W72/072Connecting or disconnecting of bump connectors
    • H10W72/07251Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/20Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps

Landscapes

  • Wire Bonding (AREA)
  • Die Bonding (AREA)

Description

【発明の詳細な説明】 [産業上の利用分野] 本発明は半導体装置を製造するために基板のパ
ツド又はリード(以下リードの場合について述べ
る)に直接チツプのバンプを重ね合せてボンデイ
ングするフエースダウン方式のチツプボンデイン
グの位置合せ方法に関する。
[Detailed Description of the Invention] [Industrial Application Field] The present invention is a face-down method in which bumps of a chip are bonded by directly overlapping the pads or leads of a substrate (the case of leads will be described below) to manufacture semiconductor devices. The present invention relates to an alignment method for chip bonding.

[従来の技術] 従来、かかるチツプボンデイングにおいて基板
のリードとチツプのバンプとの位置合せは、第5
図又は第6図に示す方法で行われている。
[Prior Art] Conventionally, in such chip bonding, the alignment between the leads of the board and the bumps of the chip was performed in the fifth step.
This is done by the method shown in FIG.

第5図の方法は、図示しないボンデイングステ
ーシヨンに位置決め保持された基板1の上方にチ
ツプ2がボンデイングツール3に吸着保持されて
位置し、基板1の下方に配設されたカメラ4によ
り基板1とチツプ2を同一画面上に写し、基板1
のリード1aとチツプ2のバンプ2aが重なるよ
うに位置合せする。図中、5はハーフミラー、6
はランプを示す。
In the method shown in FIG. 5, a chip 2 is placed above a substrate 1 which is positioned and held by a bonding station (not shown), and is held by a bonding tool 3, and a camera 4 disposed below the substrate 1 is used to detect the substrate 1. Copy chip 2 on the same screen, and
The leads 1a of the chip 2 and the bumps 2a of the chip 2 are aligned so that they overlap. In the figure, 5 is a half mirror, 6
indicates a lamp.

第6図の方法は、カメラ10及びハーフミラー
11を基板1の上方に配設し、ランプ12による
基板1の反射光及びランプ13によるチツプ2の
反射光をハーフミラー11を用いて基板1とチツ
プ2をカメラ10の同一画面上に写し、基板1の
リード1aとチツプ2のバンプ2aが重なるよう
に位置合せする。
In the method shown in FIG. 6, a camera 10 and a half mirror 11 are disposed above the substrate 1, and the light reflected from the substrate 1 by the lamp 12 and the light reflected by the chip 2 by the lamp 13 are transferred to the substrate 1 using the half mirror 11. The chip 2 is photographed on the same screen of the camera 10 and aligned so that the leads 1a of the substrate 1 and the bumps 2a of the chip 2 overlap.

[発明が解決しようとする課題] 第5図の方法は、基板1を通してチツプ2を写
し出すので、基板1が透明でないと適応できな
い。
[Problems to be Solved by the Invention] Since the method shown in FIG. 5 projects the chip 2 through the substrate 1, it cannot be applied unless the substrate 1 is transparent.

第6図の方法は、反射光によるので、基板1が
不透明であつても検知できる。しかし、この方法
はハーフミラー11の使用数を最小限にし、構造
を簡単にするには図示のように基板1の中心とチ
ツプ2の中心が垂直線上に、また基板1、チツプ
2、ハーフミラー11が水平に、更に全ての入射
角及び反射角が同一の角度θ1にそれぞれがなるよ
うにしなければならない。このため、基板1を載
置する台、ボンデイングツール3、カメラ10、
ハーフミラー11の配置が制限され、設置が困難
になる場合が生じる。また角度θ1がどれか1つで
もずれると位置ずれが生じる欠点を有する。
Since the method shown in FIG. 6 uses reflected light, it can be detected even if the substrate 1 is opaque. However, in order to minimize the number of half mirrors 11 used and to simplify the structure, this method requires that the center of the substrate 1 and the center of the chip 2 be on a vertical line, and that the center of the substrate 1, the chip 2, and the half mirror 11 must be horizontal, and all angles of incidence and reflection must be at the same angle θ 1 . For this reason, a table on which the substrate 1 is placed, a bonding tool 3, a camera 10,
The arrangement of the half mirror 11 may be restricted, making installation difficult. Furthermore, there is a drawback that if even one of the angles θ 1 deviates, a positional deviation occurs.

本発明の目的は、基板が透明、不透明にかかわ
らず適応可能で、より正確に位置合せすることが
できるチツプボンデイングの位置合せ方法を提供
することにある。
An object of the present invention is to provide a chip bonding alignment method that is applicable regardless of whether the substrate is transparent or opaque, and allows for more accurate alignment.

[課題を解決するための手段] 上記目的は、基板を基板位置決め台に載置し、
チツプをボンデイングツールで吸着させ、前記基
板位置決め台の上方に配設された基板検知用カメ
ラで基板位置決め台上の基板を写し、前記基板位
置決め台から離れた場所に配設されたチツプ検知
用カメラで前記ボンデイングツールに吸着された
チツプを写し、前記2台のカメラで取り出した2
つの映像を合成回路を用いて1つのモニタに合成
して写し出し、基板とチツプとを位置合せするこ
とにより達成される。
[Means for solving the problem] The above purpose is to place a board on a board positioning stand,
The chip is adsorbed by a bonding tool, the board on the board positioning table is photographed by a board detection camera placed above the board positioning table, and the chip detection camera is placed at a location away from the board positioning table. The chip adsorbed to the bonding tool was photographed, and the two cameras were used to take out the chip.
This is achieved by combining and displaying two images on one monitor using a combining circuit, and aligning the board and chip.

[作用] 基板とチツプとを離れた場所でそれぞれに対応
して設けられた2台のカメラで2つの映像として
取り出し、合成回路を使つて1つのモニタに合成
して写し出し、基板とチツプとを離れた場所で位
置合せする。従つて、基板が透明、不透明にかか
わらず適応できると共に、位置合せが簡単にかつ
正確に行える。またカメラを任意の位置に設置す
ることができ、またカメラの角度の設定が容易に
でき、位置ずれが生じにくくなる。
[Operation] The board and chip are captured as two images using two cameras installed in separate locations, and the composite circuit is used to combine and display the images on one monitor. Align at a remote location. Therefore, it can be applied regardless of whether the substrate is transparent or opaque, and alignment can be performed easily and accurately. Furthermore, the camera can be installed at any position, and the angle of the camera can be easily set, making it difficult for positional deviation to occur.

[実施例] 以下、本発明の一実施例を第1図乃至第4図に
より説明する。第1図に示すように、基板位置決
め台20に載置された基板1を検知する基板検知
用カメラ21と、ボンデイングツール23に吸着
保持されたチツプ2を検知するチツプ検知用カメ
ラ22とが配設されている。基板検知用カメラ2
1は基板位置決め台20の基準点A(例えばボン
デイング位置)の真上のB点に固定されている。
チツプ検知用カメラ22は回転及びXY方向に移
動可能で、基準点Aより離れたC点に配設されて
いる。ボンデイングツール23は上下(Z)と
XY方向に移動及び回転可能に設けられており、
C点の真上のD点及びA点の真上のE点に位置す
ることができる。また基板位置決め台20の前後
には基板1を基板位置決め台20に送り込み及び
送り出す基板フイーダー24が配設されている。
[Example] An example of the present invention will be described below with reference to FIGS. 1 to 4. As shown in FIG. 1, a substrate detection camera 21 that detects the substrate 1 placed on the substrate positioning table 20 and a chip detection camera 22 that detects the chip 2 held by the bonding tool 23 are arranged. It is set up. Board detection camera 2
1 is fixed at point B of the substrate positioning table 20, which is directly above the reference point A (for example, the bonding position).
The chip detection camera 22 is rotatable and movable in the X and Y directions, and is disposed at a point C that is distant from a reference point A. The bonding tool 23 has upper and lower (Z)
It is installed so that it can move and rotate in the XY directions.
It can be located at point D, which is directly above point C, and point E, which is directly above point A. Further, a substrate feeder 24 for feeding and feeding the substrate 1 to and from the substrate positioning table 20 is provided before and after the substrate positioning table 20.

前記2台のカメラ21,22は、第2図に示す
ように、タイミング回路30により偏向回路31
に設定された立上り、立下り時間の信号が入力さ
れており、カメラ21,22が映像ビームを信号
に変換し、合成回路32により2台のカメラ2
1,22からの信号を合成、増幅し、モニタ33
に入力して合成画像を写すようになつている。
The two cameras 21 and 22 are connected to a deflection circuit 31 by a timing circuit 30, as shown in FIG.
The cameras 21 and 22 convert the video beams into signals, and the synthesis circuit 32 converts the two cameras 2
The signals from 1 and 22 are combined and amplified, and the monitor 33
It is now possible to input a composite image into the image.

次に本発明の方法について説明する。まず、第
3図に示すように基板位置決め台20のA点上に
マーク40又はそれに代るものが付された2枚の
透明板41,42をそのマーク40を一致させて
収納した治具43を固定する。これを基板検知用
カメラ21で写す。当然、この状態においては2
枚の透明板41,42のマーク40は重なつてモ
ニタ33(第2図参照)に移る。
Next, the method of the present invention will be explained. First, as shown in FIG. 3, a jig 43 stores two transparent plates 41 and 42 with a mark 40 or an alternative thereon on the point A of the substrate positioning table 20 with the marks 40 aligned. to be fixed. This is photographed by the board detection camera 21. Naturally, in this state, 2
The marks 40 on the two transparent plates 41 and 42 are overlapped and transferred to the monitor 33 (see FIG. 2).

次にボンデイングツール23を電気マニピユレ
ータを用いてXY方向に移動させてA点の真上の
E点に位置させる。続いてボンデイングツール2
3を下降させて最上の透明板41を吸着させ、再
びE点に上昇又は上昇しながらXY方向に移動さ
せてD点に位置させる。この時のボンデイングツ
ール23のXY方向の距離X1、Y1をコンピユー
タ等に記憶させておく。ボンデイングツール23
がD点に位置すると、ボンデイングツール23に
吸着されている透明板41をチツプ検知用カメラ
22で写す。そこで、基板検知用カメラ21で写
している残つた透明板42とチツプ検知用カメラ
22で写している透明板41の2つの映像を第2
図に示す合成回路32を通して合成画像とし、1
台のモニタ33上に写し、透明板41,42の合
せマーク40が一致するようにチツプ検知用カメ
ラ22の位置及び倍率を調整する。基板検知用カ
メラ21の位置及び倍率はボンデイングツール2
3で透明板41を吸着する前に設定しておく。こ
れにより、2台のカメラの倍率及び位置の調整が
完了する。そこで、透明板41,42及び治具4
3を取除く。
Next, the bonding tool 23 is moved in the X and Y directions using an electric manipulator to position it at point E directly above point A. Next, bonding tool 2
3 is lowered to adsorb the uppermost transparent plate 41, and is again raised to point E, or moved in the XY direction while rising, and positioned at point D. The distances X 1 and Y 1 of the bonding tool 23 in the X and Y directions at this time are stored in a computer or the like. Bonding tool 23
When the bonding tool 23 is located at point D, the chip detection camera 22 photographs the transparent plate 41 that is attracted to the bonding tool 23. Therefore, the two images of the remaining transparent plate 42 captured by the board detection camera 21 and the transparent plate 41 captured by the chip detection camera 22 are used as a second image.
A synthesized image is created through the synthesis circuit 32 shown in the figure, and 1
The position and magnification of the chip detection camera 22 are adjusted so that the alignment marks 40 on the transparent plates 41 and 42 coincide with each other. The position and magnification of the board detection camera 21 are determined by the bonding tool 2.
The setting is made before adsorbing the transparent plate 41 in step 3. This completes the adjustment of the magnification and position of the two cameras. Therefore, the transparent plates 41, 42 and the jig 4
Remove 3.

次に第1図に示すように、実際の試料である基
板1を基板位置決め台20のA点に位置決め載置
し、チツプ2をボンデイングツール3に吸着さ
せ、基板検知用カメラ21をB点に、ボンデイン
グツール23をD点にそれぞれ位置させる。そし
て、基板1を基板検知用カメラ21で、チツプ2
をチツプ検知用カメラ22でそれぞれ写すと、第
2図に示す合成回路32を通してモニタ33上に
第4図aに示すように合成画像として写し出され
る。次にチツプ2、即ちボンデイングツール23
を回転及びXY方向に移動させ、又は基板位置決
め台20を回転及びXY方向に動作させ、同図c
に示すように基板1のリード1aとチツプ2のバ
ンプ2aとを合せる。この位置合せ方法について
は種々の方法が考えられるが、その方法について
は後述する。
Next, as shown in FIG. 1, the substrate 1, which is an actual sample, is positioned and placed on the substrate positioning table 20 at point A, the chip 2 is attracted to the bonding tool 3, and the substrate detection camera 21 is placed at point B. , the bonding tool 23 is positioned at point D, respectively. Then, the board 1 is detected by the board detection camera 21, and the chip 2 is
When each image is captured by the chip detection camera 22, a synthesized image is displayed on the monitor 33 through the synthesis circuit 32 shown in FIG. 4 as shown in FIG. 4a. Next, the tip 2, that is, the bonding tool 23
by rotating and moving in the XY directions, or rotating and moving the board positioning table 20 in the XY directions.
The leads 1a of the substrate 1 and the bumps 2a of the chip 2 are aligned as shown in FIG. Various methods can be considered for this positioning method, which will be described later.

次にボンデイングツール23を第1図の説明に
おいて定めたX1、Y1の距離移動させて基板1の
真上のE点に位置させ、続いてボンデイングツー
ル23を下降させて基板1にチツプ2を押付ける
と、基板1のリード1aにチツプ2のバンプ2a
が重ね合せられて正確にボンデイングされる。以
降、第1図において説明した動作を手動又は自動
で行い、順次ボンデイングが自動的に行われる。
Next, the bonding tool 23 is moved the distance X 1 and Y 1 determined in the explanation of FIG. When pressed, the bumps 2a of the chip 2 are pressed onto the leads 1a of the board 1.
are superimposed and bonded accurately. Thereafter, the operations explained in FIG. 1 are performed manually or automatically, and bonding is performed automatically in sequence.

次に第4図aの状態より同図cに示すように基
板1及びチツプ2を位置合せする方法を2つ説明
する。
Next, two methods for aligning the substrate 1 and the chip 2 as shown in FIG. 4C from the state shown in FIG. 4A will be explained.

第4図aにおいて、実線で示すx、yは基準の
クロスライン、一点鎖線で示すx′、y′は基板1の
基準ライン、点線で示すx″、y″はチツプ2の基
準ラインをそれぞれ示す。またθ′は基準ライン
x、yから基準ラインx′、y′の傾き、即ち基板1
の傾き角度、θ″は基準ラインx、yから基準ライ
ンx″、y″の傾き、即ちチツプ2の傾き角度をそ
れぞれ示す。そこで、θ′、θ″を求め、チツプ2又
は基板1をθ=θ″−θ′だけ回転させると、同図b
(図は基板1を回転させた状態)に示すように基
板1とチツプ2が平行になる。次にチツプ2をX
方向に△x、Y方向に△y移動(平行移動)させ
ると、チツプ2のa点はリード1aのb点に合い、
同図cに示すようにリード1aとバンプ2aが重
なる。実際はθ方向及びXY方向を同時に動か
し、第4図aの状態から1度に同図cの状態にな
る。
In Fig. 4a, x and y shown by solid lines are the reference cross lines, x' and y' shown by dashed dotted lines are the reference lines of board 1, and x'' and y'' shown by dotted lines are the reference lines of chip 2, respectively. show. Also, θ' is the slope of the reference lines x', y' from the reference lines x, y, that is, the substrate 1
The inclination angle, θ'' indicates the inclination of the reference lines x'', y'' from the reference lines x, y, that is, the inclination angle of the chip 2, respectively. Then, θ', θ'' are determined, and the chip 2 or the substrate 1 is When rotated by =θ″−θ′, the same figure b
As shown in the figure (the figure shows a state in which the substrate 1 is rotated), the substrate 1 and the chip 2 are parallel to each other. Next, X the chip 2
When moving △x in the direction and △y in the Y direction (parallel movement), point a of chip 2 aligns with point b of lead 1a,
As shown in figure c, the lead 1a and the bump 2a overlap. In reality, the θ direction and the XY direction are moved simultaneously, and the state shown in FIG. 4 a is changed to the state shown in FIG. 4 c at one time.

他の方法としては、第4図aに示すようにチツ
プ2の任意の2点a1、a2及び基板1の任意の2点
b1、b2を予め決めておく。まず、チツプ2の傾き
角度αを求める。予め決めたa1、a2の基準ライン
xy方向のずれを△x1、△y1とすると、α=tan-1
△y1/△x1となる。同様に基板1の傾き角βを求める と、β=tan-1△y2/△x2となる。従つて、基板1とチ ツプ2とのずれ角度θはθ=α−βで求まる。こ
こで、θ>0は図から見ると右回り、θ<0は図
から見ると左回りである。そこで、基板1をθ回
転させると、同図bに示すように基板1とチツプ
2が平行になる。次に予め定めたチツプ2の1点
a1と基板1の1点b1とのずれ△x、△yを検出
し、チツプ2をx軸方向に△x、y軸方向に△y
移動させると、同図cのようにリード1aとバン
プ2aが重なる。このように、予め基板1及びチ
ツプ2にそれぞれ任意の2点を決め、どの点とど
の点が対応するかを決めておけば、自動検出して
自動ボンデイングが行える。
As another method, as shown in FIG.
b 1 and b 2 are determined in advance. First, the inclination angle α of the chip 2 is determined. Predetermined reference lines for a 1 and a 2
If the deviation in the x and y directions is △x 1 and △y 1 , then α=tan -1
△y 1 / △x 1 . Similarly, when determining the tilt angle β of the substrate 1, it becomes β=tan −1 Δy 2 /Δx 2 . Therefore, the deviation angle θ between the substrate 1 and the chip 2 is determined by θ=α−β. Here, θ>0 means clockwise rotation when viewed from the figure, and θ<0 means counterclockwise rotation when viewed from the figure. Therefore, when the substrate 1 is rotated by .theta., the substrate 1 and the chip 2 become parallel to each other as shown in FIG. Next, 1 point from the predetermined chip 2
The deviation △x, △y between a 1 and one point b 1 on the board 1 is detected, and the chip 2 is moved △x in the x-axis direction and △y in the y-axis direction.
When moved, the lead 1a and the bump 2a overlap as shown in FIG. In this way, if two arbitrary points are determined in advance on each of the substrate 1 and the chip 2, and it is determined which points correspond to which points, automatic detection and automatic bonding can be performed.

なお、第3図において説明した2台のカメラ2
1,22の倍率及び位置調整は初めに一度行うの
みでよく、以降の位置合せ及びボンデイング時に
は必要としない。また倍率調整において第3図に
示すように透明板41,42に十字マーク40を
付したが、特にこれに限定されるものではなく、
三角、四角、丸のマークを付してもよく、またマ
ーク40は付さなく、透明板41,42の大きさ
を同じにし、外形で合せるようにしてもよい。ま
た実施例は、ボンデイングツール23を基板位置
決め台20の位置よりチツプ検知用カメラ22の
上方まで移動させたXY方向の位置を算出した
が、既に基板位置決め台20の位置からチツプ検
知用カメラ22の上方までの距離が予め判明して
いる時は、この距離を改めて算出させる必要がな
いことはいうまでもない。
Note that the two cameras 2 explained in FIG.
The magnification and position adjustments of 1 and 22 only need to be performed once at the beginning, and are not required during subsequent position alignment and bonding. Further, when adjusting the magnification, as shown in FIG. 3, cross marks 40 are attached to the transparent plates 41 and 42, but the present invention is not limited to this.
Triangular, square, or round marks may be attached, or the mark 40 may not be attached, and the transparent plates 41 and 42 may have the same size and match in outer shape. In addition, in the embodiment, the position in the XY direction was calculated by moving the bonding tool 23 from the position of the substrate positioning table 20 to above the chip detection camera 22, but the position of the chip detection camera 22 was already calculated from the position of the substrate positioning table 20. It goes without saying that when the distance to the top is known in advance, there is no need to calculate this distance anew.

[発明の効果] 以上の説明から明らかなように、本発明になる
チツプボンデイングの位置合せ方法によれば、基
板とチツプとを離れた場所でそれぞれに対応して
設けられた2台のカメラで2つの映像として取り
出し、合成回路を使つて1つのモニタに合成して
写し出し、基板とチツプを離れた場所で位置合せ
するので、基板が透明、不透明にかかわらず適応
できると共に、位置合せが簡単にかつ正確に行え
る。またカメラを任意の位置に設置することがで
き、またカメラの角度の設定が容易にでき、従来
技術におけるような位置ずれが生じにくくなる。
[Effects of the Invention] As is clear from the above explanation, according to the chip bonding alignment method of the present invention, two cameras installed correspondingly to the substrate and the chip can be used at separate locations. The two images are taken out, combined and displayed on a single monitor using a compositing circuit, and the board and chip are aligned at a separate location, so it can be applied regardless of whether the board is transparent or opaque, and alignment is easy. and be able to do it accurately. Furthermore, the camera can be installed at any position, and the angle of the camera can be easily set, making it difficult for positional deviations to occur as in the prior art.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例を示し、aは正面説
明図、bは斜視説明図、第2図は回路図、第3図
はカメラの倍率調整方法を示し、aは正面説明
図、bは斜視説明図、第4図a,b,cはモニタ
上に写し出された基板1とチツプ2との位置調整
を示す説明図、第5図は透明基板の場合における
従来の方法を示す説明図、第6図は不透明基板の
場合における従来の方法を示す説明図である。 1:基板、2:チツプ、20:基板位置決め
台、21:基板検知用カメラ、22:チツプ検知
用カメラ、23:ボンデイングツール、32:合
成回路、33:モニタ、40:マーク、41,4
2:透明板。
FIG. 1 shows an embodiment of the present invention, in which a is a front explanatory view, b is a perspective explanatory view, FIG. 2 is a circuit diagram, and FIG. 3 is a camera magnification adjustment method, a is a front explanatory view, b is a perspective explanatory diagram; FIGS. 4a, b, and c are explanatory diagrams showing the position adjustment of the substrate 1 and the chip 2 projected on the monitor; and FIG. 5 is an explanatory diagram showing the conventional method in the case of a transparent substrate. 6 are explanatory diagrams showing a conventional method in the case of an opaque substrate. 1: Board, 2: Chip, 20: Board positioning stand, 21: Board detection camera, 22: Chip detection camera, 23: Bonding tool, 32: Synthesis circuit, 33: Monitor, 40: Mark, 41,4
2: Transparent plate.

Claims (1)

【特許請求の範囲】 1 基板を基板位置決め台に載置し、チツプをボ
ンデイングツールで吸着させ、前記基板位置決め
台の上方に配設された基板検知用カメラで基板位
置決め台上の基板を写し、前記基板位置決め台か
ら離れた場所に配設されたチツプ検知用カメラで
前記ボンデイングツールに吸着されたチツプを写
し、前記2台のカメラで取り出した2つの映像を
合成回路を用いて1つのモニタに合成して写し出
し、基板とチツプとを位置合せすることを特徴と
するチツプボンデイングの位置合せ方法。 2 マーク入り又は同じ大きさの2個の透明板の
一方を基板位置決め台に載置し、他方をボンデイ
ングツールに吸着させ、基板位置決め台の上方に
配設された基板検知用カメラで前記基板位置決め
台上の透明板を写し、前記基板位置決め台から離
れた場所に配設されたチツプ検知用カメラで前記
ボンデイングツールに吸着された透明板を写し、
前記2台のカメラで取り出した2つの映像を合成
回路を用いて1つのモニタに合成して写し、前記
2台のカメラの倍率及び位置を調整し、次に基板
を基板位置決め台に載置し、チツプを前記ボンデ
イングツールに吸着させ、基板及びチツプを前記
2台のカメラで2つの映像として取り出し、前記
合成回路を用いて前記1つのモニタに合成して写
し出し、基板とチツプとを位置合せすることを特
徴とするチツプボンデイングの位置合せ方法。
[Claims] 1. Place the substrate on a substrate positioning table, adsorb the chip with a bonding tool, and photograph the substrate on the substrate positioning table with a substrate detection camera disposed above the substrate positioning table. A chip detection camera placed at a location away from the substrate positioning table photographs the chip adsorbed to the bonding tool, and the two images taken by the two cameras are displayed on one monitor using a compositing circuit. A chip bonding alignment method characterized by combining and projecting and aligning a substrate and a chip. 2. Place one of two transparent plates with marks or of the same size on a substrate positioning table, adsorb the other on a bonding tool, and position the substrate using a substrate detection camera disposed above the substrate positioning table. Photographing the transparent plate on the table, and photographing the transparent plate adsorbed to the bonding tool with a chip detection camera disposed at a location away from the substrate positioning table;
The two images taken by the two cameras are combined and displayed on one monitor using a composition circuit, the magnification and position of the two cameras are adjusted, and then the board is placed on a board positioning table. , the chip is adsorbed to the bonding tool, the board and the chip are taken out as two images by the two cameras, the composite circuit is used to combine and display the images on the one monitor, and the board and chip are aligned. A chip bonding alignment method characterized by the following.
JP63260449A 1988-10-18 1988-10-18 Alignment of chip bonding Granted JPH02249242A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63260449A JPH02249242A (en) 1988-10-18 1988-10-18 Alignment of chip bonding

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63260449A JPH02249242A (en) 1988-10-18 1988-10-18 Alignment of chip bonding

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP56031619A Division JPS57147245A (en) 1981-03-05 1981-03-05 Positioning method and device for chip bonding

Publications (2)

Publication Number Publication Date
JPH02249242A JPH02249242A (en) 1990-10-05
JPH039621B2 true JPH039621B2 (en) 1991-02-08

Family

ID=17348093

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63260449A Granted JPH02249242A (en) 1988-10-18 1988-10-18 Alignment of chip bonding

Country Status (1)

Country Link
JP (1) JPH02249242A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2780000B2 (en) * 1993-06-16 1998-07-23 澁谷工業株式会社 Semiconductor alignment equipment
JP2007173801A (en) * 2005-12-22 2007-07-05 Unaxis Internatl Trading Ltd Attaching the flip chip to the substrate

Also Published As

Publication number Publication date
JPH02249242A (en) 1990-10-05

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