JPH02249263A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To obtain an element isolation structure for enabling a substrate potential to be set in a thin-film MOSFET obtained by the selection polishing method by forming a connection region of wiring for setting substrate potential subjected to dielectric isolation by the use of a second field oxide film which is thinner than a first field oxide film and a MOSFET forming region. CONSTITUTION:A p-type semiconductor region 25 or an n-type semiconductor region surrounded by a first field oxide film 21 is formed at a silicon semiconductor substrate 11 and a connection region 23 of wiring for setting substrate potential of that region which is subjected to dielectric isolation by a second oxide film 22 which is at least thinner than the first field oxide film 21 and a MOSFET forming region are formed within that region. For example, an n-channel MOSFET 24 which is subjected to dielectric isolation by the second field oxide film 22 and the connection region 23 of wiring for setting substrate potential are formed within a p-type semiconductor region 25 surrounded by the first field oxide film 22. Then, after completing selective polishing with the bottom surface of the first field oxide film 21 being the stopper of polishing, an insulating film 26 is formed and a thin-film device is formed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an element isolation structure for a semiconductor integrated circuit.

[Conventional technology]

Selective polishing is performed using a processing liquid that selectively dissolves only silicon from the back side of the silicon substrate, on which devices are formed on the main surface, and a thin film device is formed by using the field oxide film of the device as a polishing stopper. (Tsuneo Hamaro, Nobuhiro Endo, Applied Physics Vol. 56, No. 11 (1987) pp141110-
1484), Figures 3(a) to 3(c) illustrate the process of selectively polishing the back surface of an n-channel MOSFET formed on a p-type silicon substrate and subsequently forming an insulating film to obtain a thin film device. FIG. Figure 3 (a
) is a cross-sectional view of an n-channel MO3FET formation region separated by a field oxide film. 11 is p
type substrate, 12 is a field oxide film, 13 is an interlayer insulating film, 14 is a source (no), 15 is a drain (no), 1
6 is the gate, 17 is Vss (0 (V)), 18 is Voo
(5(V)) There is te. FIG. 3(b) shows a device in which selective polishing was performed from the back surface of the p-type silicon substrate 11.

The selective polishing is completed at the bottom surface of the field oxide film 12 as shown in the figure, and a thin film device can be obtained by further forming an insulating film 19 on the polished surface (
Figure 3(c)).

[Problem to be solved by the invention]

Although it is possible to obtain a thin-film MOSFET device by such means, the silicon existing under the field oxide film 12 is completely removed by selective polishing, and an insulating film is further formed on the back surface.

In the case of MOSFETs for which such a substrate potential is not set, a king phenomenon and an overshoot phenomenon during switching occur due to the substrate floating effect, which hinders device design. Therefore, it is necessary to set the substrate potential of each SFET. becomes impossible.

The object of the present invention is to provide a thin film MOSFET obtained by a selective polishing method using the bottom surface of the field oxide film as a polishing stopper.
We present an element isolation structure that allows setting of the substrate potential even in ET.

[Means to solve the problem]

In order to achieve the above object, in an integrated circuit according to the present invention, a p-type semiconductor region or an n-type semiconductor region surrounded by a first field oxide film is formed in a silicon semiconductor substrate, and at least a first field oxide film is formed in the region. The connection region of the wiring for setting the substrate potential in the region dielectrically separated by the second field oxide film thinner than the field oxide film of
A 3FET formation region is formed.

[Effect]

In the present invention, the bottom surface of the thick first field oxide film acts as a stopper for selective polishing, making it possible to leave unpolished silicon under the second field oxide film even after selective polishing. It becomes possible to set the substrate potential of the MOSFET via unpolished silicon.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

(Example 1) FIG. 1(a) shows an n-channel MO3F to which the present invention is applied.
1 is a cross-sectional view showing an element isolation structure of an ET, and the same components as in FIG.
As shown in the figure, an n-channel MO3 is dielectrically isolated by a second field oxide film 22 in a p-type semiconductor region 25 surrounded by a first field oxide film 21.
A connection region 23 between the FET 24 and substrate potential setting wiring is formed. FIG. 1(b) is a cross-sectional view showing the device after selective polishing, and shows how the bottom surface of the first field oxide film 21 functions as a polishing stopper. Here, even after polishing, there is still an unpolished silicon substrate (p-type substrate) 1 under the second field oxide film 22.
1 remains. As is clear from FIG. 6, which shows a thin film device obtained by forming an insulating film 26 after selective polishing is completed in FIG. It becomes possible to set the substrate potential of each n-channel MO3FET. Therefore, even when the obtained thin film MO3FET is operated, no king phenomenon or overshoot phenomenon occurs during switching.

In the above description, the process of obtaining a thin film n-channel MOSFET by selective polishing is shown, but the present invention can also be applied to the case of obtaining a thin film p-channel MO3FET or a thin film CMOS device by selective polishing.

(Embodiment 2) FIG. 2 (&) is a process sectional view of an example in which the present invention is applied to an element isolation structure of a CMOS configuration device. That is, here, an n-type semiconductor region 38 and a P-type semiconductor region 37 surrounded by a first field oxide film 21 are formed on a p-type semiconductor substrate, and a second field oxide film 22 is further formed in the n-type semiconductor region 38. A connection region 34 for substrate potential setting wiring and a p-channel MO3FET 35 are formed, separated by a substrate potential setting wiring, and a connection region 23 for substrate potential setting wiring separated by a second field oxide film 22 is formed in the p-type semiconductor region 37.
is formed. 11 is a silicon substrate (p-type substrate);
14 is the source (n3), 15 is the drain (n”), 1
7 is Vss (0 [V)), 18 is Voo (5 (V)
), 19 is an insulating film, 31 is an n-well, 32 is a source (p
+), 33 is the drain (po). FIG. 2(b) shows a cross-sectional view of a thin film CMOS device obtained by forming an insulating film 39 on the back surface after selective polishing. As is clear from the figure, since the first field oxide film 21 is used as a stopper for selective polishing, it can be seen that the unpolished silicon substrate 11 exists under the second field oxide film 22. Therefore, it becomes possible to set the substrate potentials of the n-channel MO3FET 36 and the p-channel MO3FET 35.

〔Effect of the invention〕

As described above, if the present invention is applied, it becomes possible to set the substrate potential even in thin film MO3FET obtained by one-selective polishing method.
Even when the T is operated, the king phenomenon and the overshoot phenomenon during switching do not occur. Therefore, the thin film M
This has the effect of enabling OSFET device design.

[Brief explanation of drawings]

1(a) to 1(c) are process cross-sectional views for explaining the process of selectively polishing an n-channel ribbed 5FET to which the present invention is applied and forming a thin film device to form a backside insulating film, and FIG. a) to (c) are process cross-sectional views of an OMO3 configuration device and a thin film CMOS device to which the present invention is applied;
A) to (C) are process cross-sectional views for explaining the process of selectively polishing an n-channel MO314T having a conventional element isolation structure and forming a backside insulating film to obtain a thin film device. 11...P-type substrate 12...Field oxide film 13...Interlayer insulation a 14...Source (no) 15...Drain (n") 1
6...Kate 1'1-Vss (0(V))
18- VDD (5 [V)) 19.26.39...
Insulating film 21...first field oxide film 22...second field oxide film 23...connection area (po) 24 for substrate potential setting wiring
, 36...n-channel MO3FET 25.37
-p type semiconductor region 31...n well 32
... Source (po) 33... Drain (pl)

Claims (1)

[Claims] (1) A p-type semiconductor region or an n-type semiconductor region surrounded by a first field oxide film is formed in a silicon semiconductor substrate, and a second field oxide film that is at least thinner than the first field oxide film is formed in the region. The connection area of the substrate potential setting wiring in the area dielectrically separated by the MO
A semiconductor integrated circuit characterized in that an SFET formation region is formed.