JPH0225937A - Detecting system for cpu runaway - Google Patents

Abstract

PURPOSE:To omit the intrusion of noises into a bus line set between a ROM and a parity calculating part and to surely detect the CPU runaway by comparing a total parity given from the parity calculating part and a parity produced internally by a CPU to detect the runaway. CONSTITUTION:A parity calculating part 12 is prepared to a chip forming a ROM 11 to output a parity after totalizing the number of '1' of an input address given to the ROM 11 and the number of '1' of the output data. Furthermore an address bus 13 and a data bus 14 which connect the part 12 and the ROM 11 are also set on the same chip as these part 12 and ROM 11. As a result, both buses 13 and 14 are shortened and at the same time no noise intrudes into both buses at all. Thus the CPU runaway can be surely detected even though the noises intrudes into the buses set between the part 12 and the ROM 11.

Description

[Detailed Description of the Invention] [Summary] The present invention relates to a CPU runaway detection method that eliminates noise from entering the path line between the ROM and the parity calculation section, and
A CPU that has a function of fetching instructions or data with the purpose of ensuring runaway detection;
a ROM that stores instructions or data and provides instructions or data addressed by the CPU to the CPU;
A parity calculating section is built in the M and outputs parity by summing the input address recognized by the ROM and the corresponding output data or instruction, and the total parity from the parity calculating section and the CPU are internally calculated. It is configured to detect runaway by comparing the parity generated in

[Industrial application field]

The present invention relates to a runaway detection method for a CPU (central processing unit).

[Conventional technology]

When a device incorporating a microcomputer is operated continuously for a long period of time, it is required to be able to prevent the CPU from running out of control due to noise entering the CPU bus.

FIG. 2 is a block diagram of a conventional CPU runaway detection method.

In the figure, 1 is the CPU, 2 is the parity calculation unit, and 3 is the R
In OM these are configured separately.

The CPUI and the parity calculation section 2 are connected by an address bus 4 and a data bus 5, and the parity calculation section 2 and the ROM 3 are connected by an address bus 6 and a data bus 7.

In the conventional CPU runaway detection method configured as described above, in order to give instructions or data addressed by the CPUI from the ROM 3 to the CPU 1,
When these are taken into the latch circuit, that is, when the CPU fetches an instruction or data, the number of 1's in the address output from the CPU 1 to the parity calculation unit 2 through the address bus 4 and the number of 1's in the address output through the address bus 6 are used. By doing so, the data or instruction output from the ROM 3 to the parity calculation unit 2 through the data bus 7 is
The parity calculation unit 2 adds up the total parity calculation result and the parity internally generated by CPUI,
That is, the output address is compared with the total parity of the fetched data or instruction, and if they do not match, the CPU outputs an error signal and returns this to the reset terminal of the CPU for self-recovery, or the fetch error is detected externally. It was designed to detect CPU runaway by displaying the following.

[Problem to be solved by the invention]

In the conventional CPU runaway detection method as described above, the CPU
1. Since the parity calculation section 2 and the ROM 3 are configured separately, the lengths of the address bus and data bus connecting these two players become considerably long, and as a result, noise tends to enter the bus. In this case, since the parity calculation section 2 is provided on the bus between the cput and the ROM 3, the
Although PUI runaway detection is possible, the address bus 6 or data bus 7 connecting between the parity calculation unit 2 and the ROM 3 is
Even if noise intrudes above, it is impossible to detect CPU runaway due to this noise.

For example, if noise enters the address bus 6 from the parity calculation unit 2 to the ROM 3, the CPU
When the number of addresses output to ll l"' decreases, the ROM 3 recognizes this and outputs different data or instructions than when noise does not enter, but at this time, the number of output data "l" is the same number as when no noise enters, the total parity of the parity calculation unit 2 and the parity internally generated by the CPU, even though it is different from the desired data or instruction addressed by the CPU. (The output address and the total parity of the fetched data) match, and as a result, it is determined that there is no runaway, and there is a problem that the CPUI cannot detect the runaway.

The present invention was made to solve the above-mentioned problems.
It is an object of the present invention to provide a CPU runaway detection method that prevents noise from entering a path line between a ROM and a parity calculation unit and can ensure runaway detection.

[Means for Solving the Problems] The CPU runaway detection method according to the present invention includes a CPU10 having a function of fetching instructions or data, and a CPU10 that stores instructions or data and sends instructions or data addressed by the CPU10 to the CPU10. 1l of ROM to be given and the R
The OM 11 includes a parity calculation unit 12 that is built in and outputs parity by summing the input address recognized by the ROMII and the corresponding output data or instruction, and the total parity from the parity calculation unit 12 and the CPU 10
Runaway is detected by comparing the parity with internally generated parity.

[For production]

Since the parity calculation unit is built into the ROM, noise does not enter the address bus and data bus connecting the ROM and the parity calculation unit, and runaway detection due to CPU noise is ensured.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram of a CPU runaway detection method according to the present invention.

In the figure, 10 is a CPU (central processing unit) that controls and manages input/output devices and executes given tasks;
1 is a ROM that stores individual operating instructions and other data for the CPU10, including mask ROM, PROM, and EPROM.
, EzPROM, and is configured separately from CPU10.

The ROMII has a parity calculation unit 12 that outputs parity that is the sum of address and data, and this parity calculation unit 12 is formed on the same chip as the ROMII,
The two are connected by an internal address bus 13 and an internal data bus 14 formed on the same chip. Furthermore, the parity calculation unit 12 and the CPU 10 are connected by an address bus 15 and a data bus 16, which correspond to external buses.

Next, the operation of this embodiment configured as described above will be explained.

The general instruction fetch operation of CPU10 is as follows:
An address is output from Ul0, and the addressed instruction or data is taken into the latch circuit from the ROM 12 to be given to the CPUl0. The CPU then executes or processes the given instructions or data.

When the CPU 10 fetches an instruction or data in this way, the number of "1 degrees" of the address output from the CPU 10 through the address bus 15 to the parity calculation unit 12 and The number of data or instructions taken into the parity calculation unit 2 from the ROMII through the data internal bus 14 by being addressed is summed up in the parity calculation unit 12, and this total parity result is sent to the output line 12a.
Output from.

On the other hand, output data or instructions corresponding to the address recognized by the ROMII are transferred to the CPU via an external data bus 16.
It is taken into o. Along with this, the CPU 10 outputs the internally generated parity, that is, the total parity result of the number of "1's" of the address output by the CPU 10 itself and the number of "1's" of the fetched data or instructions, to the output line 10a. Output from.

That is, as a result of comparing the two total parity results, if it is determined that they do not match, an error signal is output to the output line 10a. This error signal is directly returned to the reset terminal tab of CPU10, thereby causing CPU10 to self-recover. Then, display it as a fetch error.

In this embodiment as described above, the number of "'1°°" of the input address to the ROM 11 and the "11+" of the output data are
The parity calculation unit 2 which outputs the parity by summing the number of ROMII is provided on the same chip that constitutes the ROMII, and the address bus 13 and data bus 14 that connect the two are also formed on the same chip. address bus 13
As the lengths of the data bus 14 and the data bus 14 become shorter, there is no intrusion of noise onto these buses, and as a result, even if noise intrudes into the bus between the ROM and the parity calculation section as in the past, the CPU will not run out of control. This can solve the problem of not being detected. In addition, runaway of the CPU10 when noise enters the path line connecting the CPUIO and the parity calculation unit 12 can be detected in the same way as in the past.

Note that the method of determining parity in the present invention is free.
Depending on the manufacturing cost of the ROM, it may be calculated each time (in this case, it is possible to add several tens of gates), but the ROM
If you want to detect even the destruction of the contents, it is sufficient to be able to program one parity bit per byte.

[Effects of the Invention] As described above, according to the present invention, there is provided an LS in which a ROM has a built-in parity calculation unit that totals the input address recognized by the ROM and the output data corresponding to the input address and outputs parity.
Since the I configuration is adopted, it is possible to prevent noise from entering the path line between the ROM and the parity calculating section, and there is also an effect that runaway detection due to noise intrusion of the CPU can be reliably detected without adding a special hardware section.

is the internal bus for addresses, is the internal bus for data, is an external address bus, is an external data bus.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a CPU runaway detection method according to the present invention. FIG. 2 is a block diagram of a conventional CPU runaway detection method. In the figure, IO is CPU and ll is ROM. 12 is a parity calculation unit;

Claims (1)

[Claims] (1) CP with the function of fetching instructions or data
U(10), and R for storing instructions or data and providing instructions or data addressed by the CPU(10) to the CPU(10).
OM (11), and a parity calculation unit (12) built in the ROM (11) that totals the input address recognized by the ROM (11) and the corresponding output data or instruction and outputs parity.
), and a runaway is detected by comparing the total parity from the parity calculation unit (12) and the parity internally generated by the CPU (10). method.