JPH03186937A - Cpu bus data diagnostic device - Google Patents

Abstract

PURPOSE:To detect the error of data fetched in CPU by inspecting the same data as that which CPU fetches. CONSTITUTION:The output of a CRC calculation part 12 and the output of a CRC storage part 14 are inputted to respective inputs of a comparison part 15 with two inputs and are compared. When they do not coincide, the comparison part 15 outputs an error signal 19. The update of a program counter in an instruction processing part 11, which shows the address of a data memory 17 is stopped by the error signal 19. When a subsequent machine cycle starts with such a state, the address of the data memory 17 which is the same as that where the error occurs, is outputted from the program counter. Thus, a retry as against the occurrence of the error is executed and the error of data fetched in CPU is detected.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a CPU bus data diagnostic device, particularly a CPU bus data diagnostic device that is built into a CPU and is capable of fetching the same lotus data again even when an error is detected in the lotus data. The present invention relates to a data diagnosis device.

(Technical Environment) In recent years, microprocessors have been developed that surpass minicomputers in terms of functionality, and the tasks that these microprocessors must accomplish have become more sophisticated.

Moreover, their use is still mostly in the field of mechatronics, where highly reliable operation in very harsh noise environments is required.

Therefore, when designing these systems, it is necessary to make efforts to suppress the generation of noise, and at the same time, it is desirable that the microprocessor itself be designed to be resistant to noise.

[Conventional technology]

As a conventional technique, there is one that performs a validity check on memory data.

Fig. 2 shows an example of a conventional technology, a harness check section 4.
The configuration of the current memory is shown below.

In the figure, a CPU, a memory, and a quality check unit 4 are connected to each other via a data bus 5. In addition to data memory, parity memory is also provided.

Explain the operation.

The correct harness is written in the harrity memory 3 in advance. When the direction of the lotus is from the CPUI to the memory, the parity check section 4 calculates parity and writes it into the parity memory 3.

Conversely, when the bus direction is from memory to CPU, parity is calculated from the data on the bus, and at the same time, validity is read from parity memory 3, the two are compared, and if they do not match, an error signal is output.

This error signal generates an interrupt to the CPUI. After that, the interrupt processing program fetches the same bus data again.

[Invention or problem to be solved]

The conventional bus data diagnostic device described above has the disadvantage that it cannot detect errors in data fetched by the CPU because it is installed outside the CPU. Also, the same <
Since it is attached outside the CPU, it has the disadvantage that it takes time and effort to create a program to fetch the same lotus data again.

[Means to solve the problem]

The CPU bus data diagnosis device of the present invention includes an instruction processing unit and a CRC calculation unit connected to each other by a data bus, and a CRC calculation unit that temporarily stores the CRC calculation calculation result and outputs it to the CR, C bus, or the CR, C bus. A CRC storage section that temporarily stores the CRC signal from the C bus and the CRC calculation calculation unit are used as first inputs, and the output of the CRC storage section is used as a second input.
As an input, there is a comparator that compares these two inputs and outputs an error signal if they do not match, and a comparator that is located inside the instruction processing section and updates its value using the error signal output from the comparator. and a program counter to be stopped.

Detailed Description of the Invention [Embodiments] Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention.

Instruction processing units 11 connected to each other by a data bus 10
and CRC calculation calculation section Upper 2 CRC calculation calculation section Upper 2 calculation results are temporarily stored and output to the CRC bus 13, or
CR that temporarily stores the CRC signal from the RC bus 13
The C storage unit 14 and the CRC calculation unit use the upper two inputs as the first input, and the output of the storage unit 14 as the second input, and compare the two inputs to see if they match. If they do not match, output an error signal. Inside the comparison unit 15 and the instruction processing unit 11,
The program counter 16 is configured to stop updating its value in response to an error signal output from the comparator 15.

Further, the data bus 10 is connected to a data memory 17, and the =5 CRC bus 13 is connected to a CRC memory 18.

Next, the operation will be explained.

Correct CRC data is written in the CRC memory 18 in advance. The direction of the data bus 10 is
When the direction is from to memory, 2RC is calculated on the CRC calculation calculation unit for the data output from the instruction processing unit 11, and the result is sent to the CRC memory 1 via the CRC path 13.
Write in 8.

When the direction of the data bus 10 is reversed, that is, from the data memory 17 to the instruction processing unit 11, the data bus 10
The above data is input into the instruction processing section 11 and the CRC calculation section in one machine cycle.

CRC Calculation Calculation Unit 2 calculates the CRC for this data. CR read out from CRC memory 18 at the same time
The C data is stored in the CRC storage section 14.

The outputs of the CRC calculation unit and the CRC storage unit 14 are input to respective inputs of a two-input comparison unit 15 and compared.

If they do not match, the comparator 5 outputs one error signal.

A block counter that does not indicate the address of the data memory 17 in the instruction processing unit] 1 receives this error signal 19.
The update will be stopped.

When the next machine cycle starts in this state, the address of the same data memory 17 that caused the error is output from the block counter. Due to this,
When an error occurs, ri) is executed.

〔Effect of the invention〕

The CPU data diagnostic device of the present invention is effective in detecting errors in the data fetched by the CPU since the CPU fetches the data and inspects the data.

Furthermore, since the program counter can be directly controlled by hardware, there is no need to create a program to fetch the same lotus data again.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a block diagram showing a conventional example. ]O...Data bus, ]1...Instruction processing unit, ]2...
・CRC calculation section, ]3...CRC lotus, 14...C
R, C storage section, 1-5... Comparison section, 16... Program counter, 17... Data memory, 18... C
R, C memory, 19...Error signal.

Claims (1)

[Claims] An instruction processing unit and a cyclic code (CRC) calculation unit are connected to each other by a data bus, and the calculation results of the CRC calculation unit are temporarily stored and output to the CRC bus, or the CRC signal from the CRC bus is CRC to be temporarily stored
a storage unit, a comparator that takes the output of the CRC calculation unit as a first input and the output of the CRC storage unit as a second input, compares these two inputs, and outputs an error signal if they do not match; and the instruction. A CPU bus data diagnostic device comprising: a program counter located inside a processing section and whose value is stopped from being updated in response to an error signal output from the comparator.