JPH02265249A - Mos-type transistor - Google Patents

Abstract

PURPOSE:To prevent hot carriers from being trapped and to enhance reliability by forming a thermal oxide film on a low-concentration impurity regions. CONSTITUTION:It is arranged that a thermal oxide film 2 whose trap level is small is situated on a low-concentration impurity region 3 of an LDD(lightly doped drain) structure; in addition, polysilicon 1 used as a gate electrode is grown on the thermal oxide film 2. As a result, an electric field is concentrated in the impurity region 3; even when hot carriers are generated, the trap level of the thermal oxide film 2 is small; in addition, even when they are trapped, the trapped carriers do not have a bad influence on a channel part because a voltage is applied forcibly to the thermal oxide film 2. Thereby, it is possible to prevent the hot carriers from being trapped and to enhance reliability of a transistor.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to MOS transistors, particularly lightly doped drain transistors.
The present invention relates to a transistor having an LDD structure (hereinafter referred to as an LDD structure).

(Prior Art) As transistors become smaller, an electric field concentrates near the drain and hot carriers are generated, causing characteristic deterioration such as threshold voltage fluctuation.

FIG. 2 shows a conventional LDD structure transistor for relaxing the electric field. In FIG. 2, 6 is polysilicon, 7 is a gate oxide film, 8 is a spacer, 9 is a
is an impurity diffusion region (low concentration), IO is an impurity diffusion region (
(high concentration), 11 is a substrate.

As shown in FIG. 2, transistors having two types of impurity concentrations and a structure in which a low concentration impurity diffusion region 9 is located on the channel side are often used.

(Problem to be Solved by the Invention) However, in the conventional LOD structure transistor described above, the generation of hot carriers is suppressed in some cases compared to previous transistors, and furthermore, the location where hot carriers are generated is located just below the spacer ( Figure 2, bottom of 8). Since this spacer is an oxide film grown in a vapor phase, there is a problem in that it has many trap levels and is easily trapped. Furthermore, since a potential is not forcibly applied to the spacer, there is a problem in that the trapped hot carriers directly affect the channel portion.

The present invention solves these conventional problems,
The purpose is to provide a highly reliable MO3 type transistor.

(Means for Solving the Problems) In order to achieve the above object, the present invention arranges for a thermal oxide film with few trap levels to be placed on the low concentration impurity region of the LDD structure, and furthermore, In this method, polysilicon that becomes the gate electrode is grown.

(Function) Therefore, according to the present invention, by forming a thermal oxide film on a low concentration impurity region, even if an electric field is concentrated in this impurity region and hot carriers are generated, the thermal oxide film is difficult to trap because it has few trap levels. Furthermore, even if trapped carriers are trapped, a voltage is forcibly applied to the thermal oxide film, so the trapped carriers will not have an adverse effect on the channel portion. Furthermore, the low concentration impurity region has a concentration gradient in the horizontal direction, and the mutual conductance does not decrease as much as when the concentration distribution is uniform.

(Embodiment) FIG. 1 shows the structure of a transistor in an embodiment of the present invention. In Figure 1, 1 is polysilicon, 2 is a gate oxide film, and 3 is an impurity diffusion region (low concentration).
, 4 is an impurity diffusion region (high concentration), and 5 is a substrate.

Next, formation of a transistor will be explained. Semiconductor substrate 5 is thermally oxidized to form gate oxide film 2.

On this gate oxide film 2, polysilicon 1, which will serve as an electrical contact, is grown. The polysilicon film above the low concentration impurity diffusion region 3 is made thinner and tapered than that above the channel portion. This thin polysilicon film does not act as an implant mask when implanting low-concentration impurities;
In addition, in the case of high-concentration impurity implantation, the film thickness is set so as to serve as an implantation mask. Next, for example, phosphorus is implanted to form a low concentration impurity diffusion region 3, and then, for example, arsenic is implanted to form a high concentration impurity diffusion region 4, thereby forming an MO8 type transistor.

(Effects of the Invention) As is clear from the above embodiments, the present invention can improve the reliability of a transistor because hot carriers are less likely to be trapped and hot carriers do not have an adverse effect on the channel portion. Furthermore, since a spacer is not required when forming a conventional LDD structure, the process of vapor phase growth and etching can be omitted.

[Brief explanation of drawings]

FIG. 1 is a structural sectional view of a transistor according to an embodiment of the present invention, and FIG. 2 is a sectional view of a conventional LDD structure transistor. 1.6... Polysilicon, 2,7... Gate oxide film, 3,9... Impurity diffusion region (low concentration),
4, 10... Impurity diffusion region (high concentration), 5, 11
... Substrate, 8 ... Spacer Figure 1 1 Polysilicon patent applicant Matsushita Electronics Co., Ltd. 5 Non-board

Claims (1)

[Claims] A MOS transistor characterized in that the cross-sectional shape of the gate electrode is not rectangular, the end film thickness of the gate electrode is thin, and a low concentration impurity diffusion region is provided under the thin electrode.