JPH0227728A - Semiconductor device - Google Patents

Abstract

PURPOSE:To reduce resistance, and to avoid a problem of improper contact by connecting titanium silicide on the sidewall of a lower layer polycrystalline silicon. CONSTITUTION:A first wiring material 109 is formed in a 2-layer laminated structure of a lower layer of polycrystalline silicon 109' doped with an N-type impurity 1000-2000Angstrom and an upper layer of molybdenum silicide 109'' 200-500Angstrom . Titanium silicide 109'' is formed on the sidewall of the silicon 109'. The material 109 is connected to source, drain 107 through a first contact hole 110 formed at part of a first interlayer insulating oxide film 108. Thus, its resistance is reduced to avoid a problem of improper contact.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application 1] The present invention relates to the structure of a semiconductor device, and more particularly to the structure of wiring.

[Prior art] Conventional semiconductor devices, especially SRAMs with a degree of integration higher than LM bits, are known as Hitachi Review VOL, 7ON No. l (1
988-2) LM bit static RAM HM
As introduced in 628128, a three-layer polycrystalline silicon structure is used.The first and second layers are polycide (a stacked structure of polycrystalline silicon and silicide), and the first layer is a gate electrode, Word line, wiring, second layer is double word line.

The cell GND wiring, wiring, and third layer are for high resistance loads.

[Problems to be Solved by the Invention] However, the above-mentioned conventional techniques still have major problems to solve. It is the material selection for the second layer of polycide. The second layer of polycide is desired to have low resistance as a wiring material, and is also desired to be thin from the viewpoint of flatness of the multilayer structure. Titanium silicide is attracting attention as a low-resistance material, but this titanium silicide is easily dissolved in hydrofluoric acid and is used to remove the natural oxide film on one surface when forming other wiring materials on titanium silicide. In an attempt to solve the problem of not being able to perform pre-cleaning with hydrofluoric acid and causing poor contact, for example, if a hydrofluoric acid-resistant silicide such as molybdenum silicide is used, the film thickness can be increased to obtain low resistance. As mentioned above, this is not preferable from the viewpoint of the multilayer structure.

Therefore, the present invention attempts to solve such problems, and its purpose is to maintain low resistance and,
An object of the present invention is to provide a semiconductor device having a wiring structure that is stable against hydrofluoric acid pre-cleaning.

L Means for Solving the Problems] The semiconductor device of the present invention is a lower polycrystalline silicon upper layer made of a hydrofluoric acid-resistant high melting point metal or its silicide, and titanium silicide is formed on the sidewalls of the lower polycrystalline silicon. It is characterized by the presence of

It is characterized by having a polycrystalline silicon structure in which titanium silicide is formed only on the side walls.

〔Example〕

Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings. FIGS. 1(a) and 1(b) are cross-sectional views of a semiconductor device according to the present invention, in which 101 is a P-type silicon substrate;
102 is an oxide film for element isolation, 103 is a gate oxide film, 1
04 is a gate electrode (laminated polycide of polycrystalline silicon 104' and molybdenum silicide 104''), 105 is a low concentration n-type impurity diffusion layer, 106 is an insulating film sidewall, and 107 is a high concentration n-type impurity diffusion layer (source/drain). ), tOS is the first interlayer insulating oxide film. 109 is the first wiring material, and in detail, as shown in FIG. Polycrystalline silicon 109' doped with impurities, upper layer 200
- 2 consisting of 500 molybdenum silicide 109″
It has a structure in which titanium silicide 109'' is formed on the side wall of the lower polycrystalline silicon layer in a layered structure, and the first
Layer M of disconnection layer #I and part of the layer 108 are provided in the first
It is connected to the source/drain 107 through a contact hole ILO. Reference numeral 111 is a high-resistance polycrystalline silicon, which is connected to the first through a second hole 113 provided in a part of the second glabella insulating oxide film 112.
It is connected to the wiring material 109 of. 114 is a second wiring material, which includes a lower layer titanium nitride 114' and an upper layer Al1.
4″ laminated structure, with a third glabellar insulating oxide film 115.
and is connected to the first wiring material 109 through a third contact hole 116 continuously formed in a part of the second glabellar insulating oxide M112; A fourth contact hole 117 continuously formed in a part of the film 115, the second glabella insulating oxide film 112, and the third interlayer insulating oxide film 1115.
It is connected to the source and drain 107 via.

Next, a method for manufacturing a semiconductor device according to the present invention, particularly a method for forming the first wiring material 109, will be described in detail. After forming the first contact hole 110, 1000-2000 polycrystalline silicon 109 is deposited on the entire surface by chemical vapor deposition.
An n-type impurity such as arsenic or phosphorus is ion-implanted into the entire surface of the 0th order where 0 is to be formed, and annealing is performed at 900-1000°C.

20" molybdenum silicide 109" by sputtering method
The molybdenum silicide 109'' and the polycrystalline silicon 109' are etched using a resist pattern.

After removing the resist pattern, 600-1000 pieces of titanium were formed using the spackle method and exposed using a halogen lamp.
By annealing at 00-800°C, the titanium reacts only with the sidewalls of the underlying polycrystalline silicon 109' (no reaction occurs on the top surface due to the presence of molybdenum silicide 109'). ″
form. Unreacted titanium is removed by etching with a mixture of ammonia and hydrogen peroxide.

Although the present invention has been specifically explained based on the embodiments above, it goes without saying that the present invention is not limited to the above embodiments, and can be modified in various ways without departing from the gist thereof.

For example, the hydrofluoric acid-resistant substance may be a high melting point metal such as Mo, Ni, Co, W, or P, or a silicide thereof, in addition to molybdenum silicide.

[Effects of the Invention] As described above, according to the present invention, the resistance can be lowered by the titanium silicide layer provided on the sidewall, and connections with other wiring materials can be made using molybdenum silicide. This has the great effect of avoiding the conventional problem of poor contact.

[Brief explanation of the drawing]

FIGS. 1(a) and 1(b) are cross-sectional views showing the structure of a semiconductor device of the present invention. 101 ・ 102 ・ 103 ・ 104 ・ 104'104'' 105 ・ 106 ・ 107 ・ ・P-type silicon substrate, oxide film for element isolation, gate oxide film, gate electrode, polycrystalline silicon, molybdenum silicide, low concentration n-type impurity diffusion Layer, insulating film sidewall, high concentration n-type impurity diffusion layer (saw drawing: 1 engraving (no change!!!) 709°' / 109' Figure 108 ・ 109 ・ 109'109'' 110 ・ 1 1, 1 ・ 112 ・ 113 ・ 114 ・ 114' 115 ・ 116 ・ 117 ・ S/Drain) First oxide film for interlayer insulation First wiring material Polycrystalline silicon Molybdenum silicide Titanium silicide First hole Crystalline silicon Second oxide film for insulation between eyebrows Second contact hole Second wiring material Titanium nitride L Third oxide film for interlayer insulation Third contact hole Fourth contact hole Applicant: Seiko Epson Corporation Agent Person Patent attorney Masatoshi Kamiyanagi (and 1 other person) Procedural amendment (method) Case description 1988 Name of patent layer invention Semiconductor device No. 177911 3゜Relationship with the person making the amendment Patent applicant◎ 163 2-4-1 Nishi-Shinjuku, Shinjuku-ku, Tokyo (236)
Seiko Epson Corporation Representative Director Nakamura
Kouya 46 Agent 7゜Contents of the amendment Engraving of the drawings originally attached to the application (no changes to the contents)

Claims (1)

[Claims] 1. A semiconductor device comprising a lower layer of polycrystalline silicon, an upper layer of a hydrofluoric acid-resistant high melting point metal or a silicide thereof, and a sidewall of the lower layer of polycrystalline silicon is formed with titanium silicide.