JPH0227730A - semiconductor equipment - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application 1] The present invention relates to the structure of a semiconductor device, and more particularly to the structure of wiring.

[Conventional technology]

Conventional semiconductor devices, especially SRAMs with a density higher than IM bits, have been described in Hitachi Review Vol.
988-2) IM bit static RAM 8M
A three-layer polycrystalline silicon structure is used as introduced in No. 628128. The 1st and 2nd layers are polycide (
(layered structure of polycrystalline silicon and silicide), and the first
The layers are for gate electrodes, word lines, and wiring; the second layer is for double word lines, cell GND wiring, and wiring; and the third layer is for high resistance loads.

[Problems to be Solved by the Invention] However, the above-mentioned prior art still leaves major problems to be solved. It is the second layer of polycide material $4 removed. The second layer of polycide is desired to have low resistance as a wiring material, and is also desired to be thin from the viewpoint of flatness of the multilayer structure. Titanium silicide is attracting attention as a low-resistance material, but titanium silicide easily dissolves in hydrofluoric acid.
When forming other wiring materials on titanium silicide,
In an attempt to solve this problem, in which pre-cleaning with hydrofluoric acid for the purpose of removing the natural oxide film on the surface cannot be performed, resulting in poor contact, for example, if a hydrofluoric acid-resistant silicide such as molybdenum silicide is used, the low In order to increase the resistance, the film thickness must be increased, which is undesirable from the standpoint of the multilayer structure, as mentioned earlier.

Therefore, the present invention attempts to solve such problems, and its purpose is to maintain low resistance and,
An object of the present invention is to provide a semiconductor device having a wiring structure that is stable against hydrofluoric acid pre-cleaning.

[Means to solve the problem]

The semiconductor device of the present invention is characterized by having a three-layer stacked wiring structure consisting of a lower layer of polycrystalline silicon, an intermediate layer of titanium silicide, and an upper layer of a hydrofluoric acid-resistant high melting point metal or its silicide.

〔Example〕

Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings. FIGS. 1(a) and 1(b) are cross-sectional views of two semiconductor devices according to the present invention, in which 101 is a P-type silicon substrate;
102 is an oxide film for element isolation, 103 is a gate oxide film, 1
04 is a gate electrode (laminated polycide of polycrystalline silicon 104' and molybdenum silicide 104''), 105 is a low concentration n-type impurity diffusion layer, 106 is an insulating film sidewall, and 107 is a high concentration n-type impurity diffusion layer (source/drain). ), 108 is the first interlayer insulating oxide film. 109 is the first wiring material. In detail, as shown in FIG. polycrystalline silicon 109' doped with impurities of 10
00-20-00 titanium silicide 109'', upper layer is 200-1000 molybdenum silicide 109''
The first contact hole 11 is formed in a part of the first glabella insulating oxide film 108.
0 to the source/drain 107.

111 is polycrystalline silicon for high resistance, and is connected to the first wiring material 109 through a second contact hole 113 provided in a part of the second oxide film 112 for interlayer insulation. l14 is a second wiring material and has a laminated structure of a lower layer titanium nitride 114' and an upper layer A114'',
The first wiring material 10 is connected to the third interlayer insulating oxide film 115 and the third contact hole 116 continuously formed in a part of the second glabellar insulating oxide film 112.
9, and the third interlayer insulating oxide film 115
, is connected to the source and drain 107 through a fourth contact hole 117 formed continuously in a part of the second glabellar insulating oxide 111112 and the first glabellar insulating oxide 111108.

Next, a method for manufacturing a semiconductor device according to the present invention, particularly a method for forming the first wiring material 109, will be described in detail.

After forming the first contact hole 110, 600 to 1000 layers of polycrystalline silicon 109' are formed on the entire surface by chemical vapor deposition. Next, n-type impurities such as arsenic or phosphorus are ion-implanted on the entire surface. Annealing is performed at 900-1000°C. 400-800 titanium, 200-80
After forming a layer of molybdenum silicide 109'' by a continuous sputtering method, a 700-800
By performing annealing at .degree. C., the titanium reacts with a portion of the polycrystalline silicon to form titanium silicide 109''.

Although the present invention has been specifically explained based on the embodiments described above, it goes without saying that the present invention is not limited to the above embodiments, and can be modified in various ways without departing from the gist of the invention. In addition to molybdenum silicide, the acidic substance may be a high melting point metal such as MOlCOlNi, W, or Pt, or a silicide thereof.

[Effects of the Invention J As described above, according to the present invention, the titanium silicide layer can reduce the resistance, and connections with other wiring materials can be made through the hydrofluoric acid-resistant molybdenum silicide. This has the great effect of avoiding the conventional problem of poor contact.

[Brief explanation of the drawing]

FIGS. 1(a) and 1(b) are cross-sectional views showing the structure of a semiconductor device of the present invention. 101 ・ 102 ・ 103 ・ 104 ・ 104'104" 105 ・ 106 ・ 107 ・ 108 ・ 109 ・ 109'109" 110 ・ 111 ・ 112 ・ 113 ・ 114 ・ ・P-type silicon substrate, oxide film for element isolation, gate oxidation Film, gate electrode, polycrystalline silicon, molybdenum silicide, low concentration n-type impurity diffusion layer, absolute ItlIl sidewall, high concentration n-type impurity diffusion layer (source/drain), first oxide film for interlayer insulation, first Wiring material, polycrystalline silicon, titanium silicide, molybdenum silicide, first contact hole, polycrystalline silicon for high resistance, second oxide film for interlayer insulation, second contact hole, second wiring material 14'14" 15 ・ 16 ・ l 7 ・ ・Titanium nitride・AL ・Third eyebrow insulating oxide film ・Third contact hole ・Fourth contact hole Applicant: Seiko Epson Corporation Representative Patent attorney Masayoshi Kamiyanagi ( (1 other person) Engraving of Ko I (1 change in content) Procedural amendment (method) 1. Indication of the case 1988 Patent application 2. Title of the invention Semiconductor packaging 1 No. 177908 3. Case of the person making the amendment Relationship Patent applicant ■ 163 2-4-1 Nishi-Shinjuku, Shinjuku-ku, Tokyo (236)
Seiko Epson Corporation Representative Director Nakamura
Tsuneya 4, Agent (b) Contact extensions 300-302 Diagram

Claims (1)

[Claims] 1. A semiconductor device having a three-layer stacked wiring structure consisting of a lower layer of polycrystalline silicon, an intermediate layer of titanium silicide, and an upper layer of a hydrofluoric acid-resistant high-melting point metal or its silicide.