JPH0227731A - semiconductor equipment - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application 1] The present invention relates to the structure of a semiconductor device, and more particularly to the structure of wiring.

[Prior art] Conventional semiconductor devices, especially SRAMs with a degree of integration higher than LM bits, are known as Hitachi Review VOL, 7ON No. l (1
988-2) LM bit static RAM 8M
As introduced in 628128, a three-layer polycrystalline silicon structure is used.6 The first and second layers are polycide (
(layered structure of polycrystalline silicon and silicide), and the first
The layers are for gate electrodes, word lines, and wiring; the second layer is for double word lines, cell GND wiring, and wiring; and the third layer is for high resistance loads.

[Problem to be solved by the invention]

However, the above-mentioned conventional techniques still have major problems to be solved. It is the material selection for the second layer of polycide. The second layer of polycide is desired to have low resistance as a wiring material, and is also desired to be thin from the viewpoint of flatness of the multilayer structure. Titanium silicide is attracting attention as a low-resistance material, but this titanium silicide easily dissolves in hydrofluoric acid, so when forming other wiring materials on titanium dinoside, it is necessary to remove the natural oxide film on the surface. In an attempt to solve the problem of not being able to perform the intended pre-cleaning with hydrofluoric acid and causing poor contact, for example, if a hydrofluoric acid-resistant silicide such as molybdenum silicide is used, the film thickness can be increased to obtain a lower resistance. As mentioned earlier, this is not preferable from the viewpoint of the multilayer structure.

Therefore, the present invention attempts to solve such problems, and its purpose is to maintain low resistance and,
An object of the present invention is to provide a semiconductor device having a stable wiring structure with respect to pre-fluid cleaning.

[Means for Solving the Problems] A semiconductor device of the present invention is characterized by having a polycrystalline silicon wiring structure in which titanium silicide is formed only on the sidewall portions.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIGS. 1(a) and 1(b) are cross-sectional views of a semiconductor device according to the present invention, in which 101 is a P-type silicon substrate;
102 is an oxide film for element isolation, 103 is a gate oxide film, 1
04 is a gate electrode (laminated polycide of polycrystalline silicon 104' and molybdenum silicide 104''), 105 is a low concentration n-type impurity diffusion layer, 106 is an insulating film sidewall, and 107 is a high concentration n-type impurity diffusion layer (source/drain). ), 108 is the first interlayer insulating oxide film. 109 is the wiring material for the first layer. This structure has a structure in which titanium silicide 109'' is formed only on the sidewalls of the polycrystalline silicon 109', and the titanium silicide 109'' is formed through a first contact hole 110 provided in a part of the first interlayer insulation oxide film 108. Source/drain 107
connected to. 111 is polycrystalline silicon for high resistance, and is connected to the first wiring material 109 through a second contact hole 113 provided in a part of the second glabellar insulating oxide film 112. 114 is a second wiring material, which has a laminated structure of a lower layer titanium nitride 114' and an upper layer Al 14-, a third glabella insulating oxide film 115, and
It is connected to the first wiring material 109 through a third contact hole 116 formed continuously in a part of the second glabellar insulating oxide 111112, and is connected to the third glabellar insulating oxide film 115. , the second interlayer insulating oxide film 1
12, and a fourth contact hole 117 continuously formed in a part of the third interlayer insulating oxide [11115]
It is connected to the source and drain 107 via.

Next, a method for manufacturing a semiconductor device according to the present invention, particularly a method for forming the first wiring material 109, will be described in detail. After forming the first contact hole 110, 1000-2000 polycrystalline silicon 109 is deposited on the entire surface by chemical vapor deposition.
Then, an n-type impurity such as arsenic or phosphorus is ion-implanted into the entire surface to form an oxide film of 100 to 2000.
Annealing is performed at 0-1000°C.

The oxide film and the polycrystalline silicon 109 are etched using a resist pattern.

After removing the resist pattern, 600-1000 pieces of titanium were formed using a sputtering method, and 700-1000 pieces of titanium were formed using a halogen lamp.
By performing annealing at 00-800° C., the titanium reacts only with the side walls of the polycrystalline silicon 109', and no reaction occurs on the top surface due to the presence of an oxide film).Titanium silicide 109'' is formed.Unreacted. Titanium is removed by etching with a mixture of ammonia and hydrogen peroxide.

Although the present invention has been specifically explained based on the embodiments above, it goes without saying that the present invention is not limited to the above embodiments, and can be modified in various ways without departing from the gist thereof.

〔Effect of the invention〕

As described above, according to the present invention, the resistance can be reduced by the titanium silicide layer provided on the sidewall, and connections with other wiring materials can be made using polycrystalline silicon itself, which is different from the conventional method. This has the great effect of avoiding the problem of poor contact.

[Brief explanation of the drawing]

FIGS. 1(a) and 1(b) are cross-sectional views showing the structure of a semiconductor device of the present invention. lot...p-type silicon substrate 102...element isolation oxide film 103...gate oxide film 104 ・ 104'104'' 105 ・ 106 ・ 107 ・ 108 ・ 109 ・ 109'109'' 110 ・ 111 ・ 112 ・113 ・ 114 ・ 114'114'' 115 ・ 116 ・Gate electrode・Polycrystalline silicon・Molybdenum silicide・Low concentration n-type impurity diffusion layer・Insulating film sidewall・High concentration n-type impurity diffusion layer S/Drain) ・First Oxide film for insulation between eyebrows, first wiring material, polycrystalline silicon, titanium silicide, first contact hole, polycrystalline silicon for high resistance, second oxide film for interlayer insulation, second contact hole, Second wiring material, titanium nitride, AL, third interlayer insulating oxide film, third contact hole (so

Claims (1)

[Claims] A semiconductor device characterized by having a polycrystalline silicon wiring structure in which titanium silicide is formed only on sidewall portions.