JPH02295192A - Multilayer printed wiring board - Google Patents

Multilayer printed wiring board

Info

Publication number
JPH02295192A
JPH02295192A JP1116619A JP11661989A JPH02295192A JP H02295192 A JPH02295192 A JP H02295192A JP 1116619 A JP1116619 A JP 1116619A JP 11661989 A JP11661989 A JP 11661989A JP H02295192 A JPH02295192 A JP H02295192A
Authority
JP
Japan
Prior art keywords
layer
power supply
via hole
earth
ground
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1116619A
Other languages
Japanese (ja)
Other versions
JPH0638552B2 (en
Inventor
Yoshitaka Morihara
森原 良隆
Tomohiko Nishida
西田 友彦
Yukio Matsushita
幸生 松下
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Electric Works Co Ltd
Original Assignee
Matsushita Electric Works Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Works Ltd filed Critical Matsushita Electric Works Ltd
Priority to JP1116619A priority Critical patent/JPH0638552B2/en
Publication of JPH02295192A publication Critical patent/JPH02295192A/en
Publication of JPH0638552B2 publication Critical patent/JPH0638552B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

PURPOSE:To increase the density of interconnection and moreover upgrade high frequency characteristics without increasing inductance by connecting one circuit with the other circuit installed on the surfaces on the both sides of a multilayer printed board with a connection VIA hole designed to penetrate and insulated part between a power supply circuit layer and an earth circuit layer. CONSTITUTION:An edge section where a power supply circuit layer 2 is adapted to face an earth circuit layer 3, is zigzag-shaped and provided with a zigzag-shaped insulated section 9 between the power supply circuit 2 and the earth circuit layer 3. An electric power side terminal for an electronic components 4 on a layer L1 is connected with the power supply circuit layer 2 on a layer L2 by way of a power supply VIA hole 5a which penetrates an insulation layer 1a while an earth side terminal on the layer L1 is connected with the earth circuit layer 3 on the layer L2 by way of an earth VIA hole 5b which penetrates the insulation layer 1a. The power supply side terminal for the electronic component 4 on a layer L4 is connected with the power supply layer on a layer L3 by way of the power supply VIA hole 5a which penetrates an insulation layer 3c while the earth side terminal for the electronic component on the layer L4 is connected with the earth circuit layer 3 on the layer L2 by way of an earth VIA hole 5b which penetrates the insulation layer c.

Description

【発明の詳細な説明】 【産業上の利用号野1 本発明は4M以上の多層プリント配線板に関し、詳しく
は内層の″ll源層やアース層と表面の電子部品や回路
とを接続したり、上下の表面の回路を接続したりする技
術に関するものである、r従米の技術1 従米、多層プリント配線板の一例である4/l!Iプリ
ント配線板は第3図に示すように3Nの絶縁層1 at
 1 b. 1 cの2つの眉間に夫々電源層(vcc
71)2とアース層(G N D層)3とを別々に設け
ている。
[Detailed Description of the Invention] [Industrial Application No. 1] The present invention relates to a multilayer printed wiring board of 4M or more, and more specifically, the invention relates to a multilayer printed wiring board of 4M or more. The 4/l!I printed wiring board, which is an example of a multilayer printed wiring board, is a 3N printed wiring board, which is an example of a multilayer printed wiring board. Insulating layer 1 at
1 b. 1 The power supply layer (vcc
71) 2 and a ground layer (GND layer) 3 are provided separately.

つまり絶縁/W1aと絶縁1@1bとの間に電源層2を
設け、絶縁N1bと絶緑/tl 1 cとの間に7ース
層3を設けてある。そして絶Ji /l 1 a及び絶
M層1cの表面側に配置した電子部品4と電源層2及び
アース層3とを夫々電源用ヴ7イ7ホール5a’及びア
ース用ヴ7イ7ホール5b’ を介して接続している。
That is, a power layer 2 is provided between the insulation /W1a and the insulation 1@1b, and a 7-base layer 3 is provided between the insulation N1b and the insulation /tl 1 c. Then, the electronic components 4, the power supply layer 2, and the ground layer 3 arranged on the surface side of the ZI/l 1a and ZETM layers 1c are connected to the power supply V7-7 hole 5a' and the ground V7-7 hole 5b, respectively. ' are connected via.

また上下の表面の回路7間も接続用ヴアイアホール8′
にて接続している。
There is also a connecting via hole 8' between the circuits 7 on the upper and lower surfaces.
It is connected at.

[発明が解決しようとする課題] ところで、上記従未例にあっては、2つの層間に別々に
電源層2と7−六M!J3とを設けてあるため、絶ji
llaの表面側に設けた電子部品4と7ース層3とは電
源層2を貫通して7−入用ヴアイアホール5b′にて接
続しなければならなく、絶縁層1cの表面側に設けた電
子部品4と電mM2とはアース層3を貫通して電源用ヴ
アイアホール5a’にて接続しなければならない。この
ためヴTイ7ホール5a’.5b’ を電源層2やアー
ス層3に貫通させる部分には電i8X層2やアース層3
に絶縁のためのクリアランス6を設けなければならなく
、構造が複雑になると共に配線密度が低くなるという問
題があり、しかも電[1]2やアースIrII3にヴア
イアホール5a’,SL+″を貫通させるためイングク
タンス分が増加するという問題があった。
[Problems to be Solved by the Invention] By the way, in the above conventional example, the power supply layers 2 and 7-6M! are separately provided between the two layers. J3 is provided, so there is no need to
The electronic component 4 and the 7-base layer 3 provided on the surface side of the lla must pass through the power supply layer 2 and be connected at the 7-use via hole 5b', which is provided on the surface side of the insulating layer 1c. The electronic component 4 and the electric current mM2 must pass through the ground layer 3 and be connected through the power supply via hole 5a'. For this reason VTI 7 hole 5a'. 5b' is passed through the power supply layer 2 and the earth layer 3, the electric i8X layer 2 and the earth layer 3 are
It is necessary to provide a clearance 6 for insulation between the wires, which complicates the structure and lowers the wiring density.Moreover, because the wire holes 5a' and SL+'' are passed through to the electric [1] 2 and the earth IrII3, There was a problem that the inctance increased.

また上下の回路7を接続するため電源層2やアースN3
を貫通するように接続用ヴアイアホール8′を設ける(
この場合も電源ノー2やアース層3との絶縁のためクリ
アランスを設ける)ためこの点でもイングクタンス分が
増加するという問題があった。
In addition, to connect the upper and lower circuits 7, the power layer 2 and ground N3
A connecting via hole 8' is provided so as to penetrate through the (
In this case as well, since a clearance is provided for insulation from the power source 2 and the ground layer 3), there is also a problem in that the inductance increases.

本発明は叙述の点に鑑みてなされたものであって、本発
明の目的とするところは簡単な構造で電源層やアース層
と表面の電子部品や回路とを接続できると共に配線密度
を上げることがで慇、しかもインダクタンス分を増加さ
せないで高周波特性を向上できる多層プリント配線板を
提供するにある。
The present invention has been made in view of the above points, and an object of the present invention is to connect a power supply layer and a ground layer to electronic components and circuits on the surface with a simple structure, and to increase wiring density. It is an object of the present invention to provide a multilayer printed wiring board that can improve high frequency characteristics without increasing inductance.

[課題を解決するための手段1 上記目的を達成するため本発明多層プリント配線板は、
複数ノーの絶縁層1 a, 1 b. 1 cの層間に
おいて同一の眉間に電源層2とアース71]3とを分離
して設け、表面の電子部品4や回路7と上記′IL源層
2や7−スN3とを電源用ヴアイ7ホール5a及びアー
ス用ヴ7イアホール5bを介して夫々接続し、上下の表
面の回路7間を、電源/i12とアース/913との開
の絶縁部分を貫通するように設けた接続用ヴァイアホー
ル8にて接続して成ることを特徴とする。
[Means for Solving the Problems 1 To achieve the above object, the multilayer printed wiring board of the present invention has the following features:
Multiple insulating layers 1 a, 1 b. The power supply layer 2 and the ground 71] 3 are provided separately between the same eyebrows between the layers of 1c, and the electronic components 4 and circuits 7 on the surface and the above-mentioned IL source layer 2 and 7-3 are connected to the power source layer 2 and the ground 71] Connecting via hole 8 is connected through hole 5a and ground via hole 5b, and is provided between the circuits 7 on the upper and lower surfaces so as to penetrate through the open insulating part between power supply /i12 and earth /913. It is characterized by being connected at.

[作用1 同一の層闇に形成された電a層2や7−ス/13と表面
の電子部品4や回路7とを夫々電源用ヴアイアホール5
a及びアース用ヴアイアホール5bにて接続でき、従米
のように電源M2やアース/13を貫通する電源用ヴア
イ7ホールやアース用ヴアイ7ホールを要せず接続でき
て構造を簡単にできると共に配線密度を上げることがで
きる。電源用ヴ7イアホール5aやアース用ヴァイアホ
ール5bや接続用ヴアイアホール8を電源層2やアース
層3に貫通しないように設けることができてイングクタ
ンス分の増加をなくして高周波特性を向上できる. [実施例] 以下本発明の多層プリント配線板の一例としての4層プ
リント配線板の実施例により説明する。
[Function 1] The electric a layer 2 and 7-s/13 formed in the same layer and the electronic components 4 and circuit 7 on the surface are connected to the power supply via hole 5, respectively.
A and grounding via holes 5b can be connected, and the connection can be made without the need for power supply via hole 7 and ground via hole 5b that pass through power supply M2 and ground/13 as in the conventional case, simplifying the structure and increasing wiring density. can be raised. The power supply via hole 5a, the ground via hole 5b, and the connection via hole 8 can be provided so as not to penetrate the power supply layer 2 and the earth layer 3, thereby eliminating an increase in inductance and improving high frequency characteristics. [Example] An example of a four-layer printed wiring board as an example of the multilayer printed wiring board of the present invention will be described below.

両面金属箔張り積層板Aの上下両面に片面金属箔張り積
層板Bを積層して3者をプリプレグCにて接着して4層
積層板が形成され、弟1図に示すように3Nの絶縁層1
 at 1 b, 1 cと4/!1の金属M層を有し
ている。両面金属箔張り積層板Aは両面銅張り〃ラスエ
ボキシや両面銅張りガラスポリイミドなど樹脂積層板を
基板として両面に金属箔を積層したものであり、片面金
属張り積層板Bは片面鋼張りガラスエボキシや片面銅張
りガラスポリイミドなど樹脂積層板を基板として片面に
金属箔を積層しだらのである。絶縁層1aと絶縁層1b
との間の金属箔のL2/1は左右に分i!fl1されて
右側に電源屑(VCCI)2を左側にアース!(GND
層)3を設けてある。絶縁層1bと絶ji f@ 1 
cとの開の會属箔のLj層も左右に分割されて左側に電
源/!2を、右側に7一スNJ3を設けてある。電源N
2及びアースN3の対向する端縁はノグザグ状になって
いて電源N2とアース/13との間にノグザグ状の絶縁
部分9を設けてある。絶縁層1a及びM緑層1cの表面
側の金属箔のL.,L.層には適宜パターンの回路7を
設けてあり、表面側の適所に電子部品4を搭載してある
。この電子部品4は例えばメモリー素子のようなサー7
エイスマウントデバイスであり、メモリー素子の場合に
は多数個並行に列設される。L,屑の電子部品4とL2
層の電源層2やアースNj3とは夫々電気的に接続され
、[,,層の電子部品4とL,/1の電a/12やアー
ス/[3とは夫々電気的に接続されている。っまりL.
1r1の電子部品4の電源側端子とL2/Iの電源I饅
2とは絶縁N1aを貫通する電源用ヴアイアホール(v
ia Iiole) 5 aにて接続され、Ll71の
電子部品4のアースm端子とL2NJのアース層3とは
絶縁層1aを貫通するアース用ヴTイ7ホール(via
 hole)5bにて接続され、L,層の電子部品4の
電源側端子とL3層の電源層2とは絶縁層ICを貫通す
る電源用ヴ7イ7ホール5aにて接続され、L,層の電
子部品4のアース側端子とL,層のアース層3とは絶#
it/l 1 cを貫通する7−ス用ヴァイアホール5
bにて接続されている。本実施例の場合電源用ヴアイア
ホール5aやアース用ヴアイアホール5bとしてI V
 H(interstitial via hole)
を用いているが、IVH以外にヴアイアホールとして通
常のスルーホール(スルーホールを穿孔してスルーホー
ルメッキした)を用いても、その他のこれと同種の接続
方法を用いてもよい。Ll/lm及びL,層に搭載され
た電子部品4は適宜表面の回路7と接続される。また上
下の表面の回路7は接続用ヴアイアホール8にて接続さ
れるが、この接続用ヴァイアホール8は電源ffi2と
アースM3との間の絶縁部分9を貫通するように設けら
れる。この接続用ヴァイアホール8として本実施例の場
合通常のスルーホール(スルーホールを穿孔してスルー
ホールメツキした)を用いているが、IVHでもその他
の同種の接続方法を用いてもよい。
Single-sided metal foil clad laminate B is laminated on both the upper and lower surfaces of double-sided metal foil clad laminate A, and the three are bonded together with prepreg C to form a 4-layer laminate, with 3N insulation as shown in Figure 1. layer 1
at 1 b, 1 c and 4/! It has one metal M layer. Double-sided metal foil-clad laminate A is a resin laminate such as double-sided copper-clad lath epoxy or double-sided copper-clad glass polyimide, and metal foil is laminated on both sides, while single-sided metal-clad laminate B is one-sided steel-clad glass epoxy, The substrate is a resin laminate such as glass polyimide with copper cladding on one side, and metal foil is laminated on one side. Insulating layer 1a and insulating layer 1b
L2/1 of the metal foil between the left and right is minutes i! After being fl1, ground the power supply (VCCI) 2 on the right side and ground it on the left side! (GND
Layer) 3 is provided. Insulating layer 1b and insulation layer 1
The Lj layer of the foil associated with c is also divided into left and right, with the power supply on the left /! 2, and 71st NJ3 on the right side. Power supply N
The opposing edges of N2 and N3 have a nogzag shape, and a nogzag insulating portion 9 is provided between the power supply N2 and the ground N3. L. of the metal foil on the surface side of the insulating layer 1a and the M green layer 1c. ,L. A suitably patterned circuit 7 is provided on the layer, and electronic components 4 are mounted at appropriate locations on the surface side. This electronic component 4 is, for example, a server 7 such as a memory element.
It is an eighth mount device, and in the case of memory devices, many devices are arranged in parallel. L, scrap electronic parts 4 and L2
The power supply layer 2 and the ground Nj3 of the layer are electrically connected, respectively, and the electronic component 4 of the [,, layer L, /1 and the electrical a/12 and the ground /[3 are electrically connected, respectively. . Tmari L.
The power supply side terminal of the electronic component 4 of 1r1 and the power supply terminal 2 of L2/I are connected to the power supply via hole (v
The ground m terminal of the electronic component 4 of Ll71 and the ground layer 3 of L2NJ are connected through a grounding hole (via Iiole) 5a that penetrates the insulating layer 1a.
The power supply side terminal of the electronic component 4 of the L, layer and the power supply layer 2 of the L3 layer are connected to the power supply V7I7 hole 5a that penetrates the insulating layer IC, and the power supply side terminal of the electronic component 4 of the L, layer The ground side terminal of the electronic component 4 and the ground layer 3 of the L layer are disconnected.
Via hole 5 for 7-s through it/l 1 c
It is connected at b. In this embodiment, IV is used as the power supply via hole 5a and the ground via hole 5b.
H (interstitial via hole)
However, in addition to IVH, a normal through hole (a through hole formed by drilling and through hole plating) may be used as the via hole, or other similar connection methods may be used. The electronic components 4 mounted on the Ll/lm and L layers are appropriately connected to the circuit 7 on the surface. Further, the circuits 7 on the upper and lower surfaces are connected by a connecting via hole 8, and this connecting via hole 8 is provided so as to penetrate an insulating portion 9 between the power source ffi2 and the ground M3. In this embodiment, a normal through hole (a through hole is drilled and plated) is used as the connection via hole 8, but other similar connection methods may be used for IVH.

なお上記実施例では電′Ia層2やアース層3を電子部
品4に電源用ヴアイアホール5aやアース用ヴァイアホ
ール5bにて接続する実施例について述べたが、電源層
2やアース層3と表面の回路7とを接続する必要がある
場合には同様に電源用ヴアイアホールやアース用ヴアイ
アホールにて接続できる。また上記実施例では4Nプリ
ント配線板の実施例について述べたが、4層より多い多
層の多層プリント配線板にも同様に実施できる。
In the above embodiment, the power layer 2 and the ground layer 3 are connected to the electronic component 4 through the power supply via hole 5a and the ground via hole 5b. If it is necessary to connect it to the circuit 7, it can be similarly connected using a power supply via hole or a ground via hole. Further, in the above embodiments, a 4N printed wiring board has been described, but the present invention can be applied to a multilayer printed wiring board having more than four layers.

[発明の効果1 本発明は叙述の如く複数層の絶I&層の眉間において同
一の眉間に電源層とアース層とを分離して設け、表面の
電子部品や回路と上記電源層やアース層とを電源用ヴア
イアホール及びアース用ヴアイアホールを介して夫々接
続しているので、内層の同一の層に設けた電源層やアー
ス層と表面側の電子部品や回路とを同一の絶縁層に貫通
する電源用ヴアイアホール及びアース用ヴアイアホール
にて接続できるものであって、従米のように電源層やア
ース層を貫通する電源用ヴ7イ7ホールやアース用ヴァ
イアホールを要せず接続できて従来に比べて構造を簡単
にできるものであると共に従来のよ)に電源層やアース
層に貫通する部分に絶縁のためのクリアランスを設けた
りする必妥がな《て配MA密度を上げることができるも
のであり、また電源用ヴァイアホールやアース用ヴァイ
アホールが電源層やアース層を貫通しないのでイングク
タンス分の増加の防止ができ、しかも上下の表面の回路
間を、電a層とアース層との間の絶縁部分を貫通するよ
うに設けた接続用ヴアイアホールにて接続しているので
、接続用ヴアイアホールが電源層やアース層を貫通せず
イングクタンス分の増加を防止でき、イングクタンス分
の増加を防止することにより商周波特性を向上できるも
のであり、さらに電源用ヴァイアホールやアース用ヴア
イアホールや接続用ヴTイアホー.ルが電源層やアース
層を貫通しないので上下層のシールド効果を向上させる
ことができるものである。
[Effects of the Invention 1] As described above, the present invention provides a power layer and a ground layer separately in the same space between the eyebrows of a plurality of insulation layers, and connects electronic components and circuits on the surface with the power layer and the ground layer. are connected through the power supply via hole and the ground via hole, respectively, so that the power supply layer and ground layer provided on the same inner layer and the electronic components and circuits on the surface side are connected through the same insulating layer. It can be connected with a via hole and a grounding via hole, and it can be connected without the need for a power supply via hole or a grounding via hole that penetrates the power supply layer and ground layer as in the conventional case, and the structure is better than conventional ones. It is possible to increase the MA density without having to provide clearance for insulation at the part that penetrates the power supply layer or the ground layer, as is the case with conventional methods. In addition, since the power supply via hole and the grounding via hole do not penetrate the power supply layer or the ground layer, an increase in inductance can be prevented. Moreover, between the circuits on the upper and lower surfaces, the insulation between the electrical A layer and the ground layer can be prevented. Since the connection is made with a connecting via hole provided to penetrate the parts, the connecting via hole does not penetrate the power supply layer or the ground layer, preventing an increase in inductance. The commercial frequency characteristics can be improved by using the power supply via hole, the grounding via hole, and the connection via hole. The shielding effect of the upper and lower layers can be improved because the conductor does not penetrate through the power supply layer or the ground layer.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例の断面図、第2図は同上の電
源層やアース層部分を示す平面図、tJtJ3図は従未
例の断面図であって、1 a, 1 b, 1 cは絶
縁層、2は電源層、3はアース層、4は電子部品、5a
はTrL源用ヴアイアホール、5bはアース用ヴァイア
ホール、7は回路、8は接続用ヴァイアホールである。 代理人 弁理士 石 田 艮 七 第2図 手続相1正書(自発) 平成2年2月10日 1). 明細書を別紙訂正明細書の通り訂正致しま2). 図面中第1図を別紙の通り訂正致します。 平成1年特許願第1]6619号 2.発明の名称 多層プリント配線板
FIG. 1 is a sectional view of an embodiment of the present invention, FIG. 2 is a plan view showing the power supply layer and ground layer portions of the same, and FIG. tJtJ3 is a sectional view of the conventional example. 1 c is an insulating layer, 2 is a power layer, 3 is a ground layer, 4 is an electronic component, 5a
5b is a via hole for a TrL source, 5b is a grounding via hole, 7 is a circuit, and 8 is a connecting via hole. Agent Patent Attorney Ai Ishida 7 Figure 2 Procedures Minister 1 official document (self-motivated) February 10, 1990 1). We have corrected the specification as shown in the attached revised specification 2). Figure 1 of the drawings will be corrected as shown in the attached sheet. 1999 Patent Application No. 1] No. 6619 2. Name of invention Multilayer printed wiring board

Claims (1)

【特許請求の範囲】[Claims] [1]複数層の絶縁層の層間において同一の層間に電源
層とアース層とを分離して設け、表面の電子部品や回路
と上記電源層やアース層とを電源用ヴァイアホール及び
アース用ヴァイアホールを介して夫々接続し、上下の表
面の回路間を、電源層とアース層との間の絶縁部分を貫
通するように設けた接続用ヴァイアホールにて接続して
成ることを特徴とする多層プリント配線板。
[1] Separately provide a power layer and a ground layer between the same layers of multiple insulating layers, and connect electronic components and circuits on the surface to the power layer and ground layer through power supply via holes and ground vias. A multilayer structure characterized in that the circuits on the upper and lower surfaces are connected through holes, and the circuits on the upper and lower surfaces are connected through connection via holes provided to penetrate the insulating part between the power supply layer and the ground layer. printed wiring board.
JP1116619A 1989-05-10 1989-05-10 Multilayer printed wiring board Expired - Lifetime JPH0638552B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1116619A JPH0638552B2 (en) 1989-05-10 1989-05-10 Multilayer printed wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1116619A JPH0638552B2 (en) 1989-05-10 1989-05-10 Multilayer printed wiring board

Publications (2)

Publication Number Publication Date
JPH02295192A true JPH02295192A (en) 1990-12-06
JPH0638552B2 JPH0638552B2 (en) 1994-05-18

Family

ID=14691670

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1116619A Expired - Lifetime JPH0638552B2 (en) 1989-05-10 1989-05-10 Multilayer printed wiring board

Country Status (1)

Country Link
JP (1) JPH0638552B2 (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61226991A (en) * 1985-03-30 1986-10-08 日本メクトロン株式会社 Multilayer circuit board
JPS62241396A (en) * 1986-04-14 1987-10-22 日本電気株式会社 Multilayer printed wiring board

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61226991A (en) * 1985-03-30 1986-10-08 日本メクトロン株式会社 Multilayer circuit board
JPS62241396A (en) * 1986-04-14 1987-10-22 日本電気株式会社 Multilayer printed wiring board

Also Published As

Publication number Publication date
JPH0638552B2 (en) 1994-05-18

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