JPH0229540U - - Google Patents

Info

Publication number
JPH0229540U
JPH0229540U JP1988108790U JP10879088U JPH0229540U JP H0229540 U JPH0229540 U JP H0229540U JP 1988108790 U JP1988108790 U JP 1988108790U JP 10879088 U JP10879088 U JP 10879088U JP H0229540 U JPH0229540 U JP H0229540U
Authority
JP
Japan
Prior art keywords
resin layer
lead wire
circuit board
support plate
thin lead
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1988108790U
Other languages
English (en)
Other versions
JPH0627958Y2 (ja
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1988108790U priority Critical patent/JPH0627958Y2/ja
Publication of JPH0229540U publication Critical patent/JPH0229540U/ja
Application granted granted Critical
Publication of JPH0627958Y2 publication Critical patent/JPH0627958Y2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/015—Manufacture or treatment of bond wires
    • H10W72/01515—Forming coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/921—Structures or relative sizes of bond pads
    • H10W72/926—Multiple bond pads having different sizes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/753—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between laterally-adjacent chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Description

【図面の簡単な説明】
第１図は本考案の一実施例に係わる電力用ハイ
ブリツドＩＣを示す第２図の―線縦断面図、
第２図は第１図の電力用ハイブリツドＩＣの平面
図、第３図は第１図の電力用ハイブリツドＩＣを
使用したスイツチングレギユレータを示す回路図
、第４図は従来の電力用ハイブリツドＩＣを示す
平面図、第５図は第４図の―線断面図である
。 １…支持板、２…パワートランジスタチツプ、
４〜８…外部リード、３１…回路基板、３２…リ
ード細線、３５…保護樹脂、３６…樹脂封止体。

Claims (1)

  1. 【実用新案登録請求の範囲】 支持板と、該支持板の一端側に配置された外部
    リードと、前記支持板に固着された半導体素子及
    び回路基板とを有し、前記半導体素子が前記外部
    リードに対してリード細線を介して接続されてお
    り、前記支持板及び前記外部リードの端部が外囲
    体によつて被覆されている半導体装置において、 前記リード細線は前記回路基板に対して少なく
    とも２点で固着されており、前記回路基板の上面
    には前記リード細線の前記２点を両端とする区間
    を被覆するように第１の樹脂層が形成されており
    、前記第１の樹脂層の外周側には前記リード細線
    の前記区間を除く部分を被覆する前記外囲体の一
    部もしくは前記外囲体とは異なる第２の樹脂層が
    形成されており、前記第１の樹脂層の熱伝導性が
    前記第２の樹脂層の熱伝導性よりも低いことを特
    徴とする半導体装置。
JP1988108790U 1988-08-18 1988-08-18 半導体装置 Expired - Lifetime JPH0627958Y2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1988108790U JPH0627958Y2 (ja) 1988-08-18 1988-08-18 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1988108790U JPH0627958Y2 (ja) 1988-08-18 1988-08-18 半導体装置

Publications (2)

Publication Number Publication Date
JPH0229540U true JPH0229540U (ja) 1990-02-26
JPH0627958Y2 JPH0627958Y2 (ja) 1994-07-27

Family

ID=31344457

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1988108790U Expired - Lifetime JPH0627958Y2 (ja) 1988-08-18 1988-08-18 半導体装置

Country Status (1)

Country Link
JP (1) JPH0627958Y2 (ja)

Also Published As

Publication number Publication date
JPH0627958Y2 (ja) 1994-07-27

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