JPH02307253A - Resin-sealed semiconductor device - Google Patents
Resin-sealed semiconductor deviceInfo
- Publication number
- JPH02307253A JPH02307253A JP1129162A JP12916289A JPH02307253A JP H02307253 A JPH02307253 A JP H02307253A JP 1129162 A JP1129162 A JP 1129162A JP 12916289 A JP12916289 A JP 12916289A JP H02307253 A JPH02307253 A JP H02307253A
- Authority
- JP
- Japan
- Prior art keywords
- island
- center
- semiconductor pellet
- resin
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/075—Connecting or disconnecting of bond wires
- H10W72/07551—Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting
- H10W72/07554—Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting changes in dispositions
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は樹脂封止型の半導体装置に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a resin-sealed semiconductor device.
従来の樹脂封止型半導体装置は、第3図(a)。 A conventional resin-sealed semiconductor device is shown in FIG. 3(a).
(b)に示すように、アイランド3はリードフレーム外
枠11に4本の吊りリード4で連結され、アイランド3
の周囲には、アイランド3から約1m rn Hれて内
部リード5か配置され、アイランド3上にはアイランド
3の外形とほぼ同じ寸法で中央部に孔12と、上面にプ
リント配線8を有した基板2が接着剤等で固着されてい
た。アイランド3の中央上面には半導体ペレット1が接
着剤で固着され、半導体ペレット1と外部リード6とは
、基板2上面のプリント配線8と内側ボンディング線9
と外側ボンディング線10を介して接続されていた。As shown in (b), the island 3 is connected to the lead frame outer frame 11 with four hanging leads 4.
An internal lead 5 is arranged around the island 3 at a distance of about 1 m rn H, and on the island 3 there is a hole 12 in the center with approximately the same dimensions as the outer shape of the island 3, and a printed wiring 8 on the top surface. The substrate 2 was fixed with adhesive or the like. A semiconductor pellet 1 is fixed to the upper center surface of the island 3 with an adhesive, and the semiconductor pellet 1 and the external lead 6 are connected to the printed wiring 8 on the upper surface of the substrate 2 and the inner bonding wire 9.
and was connected via an outer bonding wire 10.
上述した従来の樹脂封止型半導体装置は、樹脂封止部の
面積に対する基板及びアイランドの占める割合が65〜
75%と高く、しかもアイランド及び基板は、吊りリー
ド4本でしかリードフレーム外枠に1呆持されていない
ため、樹脂封止時の溶耐樹脂の抵抗を受けやすい構造と
なっていた。そのため、樹脂封止時に溶融した樹脂か硬
化するにつれて、アイランド及び基板を押し上げあるい
は押し下げるため、基板と内部リードとを接続したボン
ディング線の変形又は断線が発生したり、ボンディング
線か樹脂表面に露出したり、あるいはアイランド下面が
樹脂下面に露出し、組立歩留りや、信頼性を低下させる
という欠点があった。In the above-mentioned conventional resin-sealed semiconductor device, the ratio of the substrate and island to the area of the resin-sealed portion is 65 to 65.
This was as high as 75%, and since the island and the board were only supported by four hanging leads to the outer frame of the lead frame, the structure was susceptible to resistance from the melt-resistant resin during resin sealing. Therefore, as the molten resin hardens during resin sealing, it pushes up or down the island and the board, causing deformation or disconnection of the bonding wires connecting the board and internal leads, or exposing the bonding wires to the resin surface. Otherwise, the lower surface of the island may be exposed to the lower surface of the resin, resulting in lower assembly yield and reliability.
本発明の樹脂封止型半導体装置は、中央部に半導体ペレ
ットを搭載するアイラン1へと、前記アイランドの周囲
に配列して設けた内部リードと、中央部に前記半導体ペ
レットの外径より僅かに大きい孔を有して前記アイラン
ドの周縁部及び前記内部リードの先端部を接着して固定
し且つ表面に配線を有する絶縁性基板と、前記半導体ペ
レットと前記配線との間を接続す乞内側ボンディング線
と、前記配線と前記内部リードとの間を接続する外側ボ
ンディング線とを有する。The resin-sealed semiconductor device of the present invention has internal leads arranged around the island to an island 1 on which a semiconductor pellet is mounted in the center, and internal leads arranged in a manner slightly smaller than the outer diameter of the semiconductor pellet in the center. inner bonding for connecting between an insulating substrate having a large hole, bonding and fixing the peripheral edge of the island and the tip of the internal lead, and having wiring on the surface, and the semiconductor pellet and the wiring; and an outer bonding line connecting between the wiring and the internal lead.
次に、本発明の実施例について図面を参照してJ(a明
する。Next, embodiments of the present invention will be explained with reference to the drawings.
第1図(a)、(b)は本発明の一実施例を示す一部切
欠平面図及び断面図である。FIGS. 1(a) and 1(b) are a partially cutaway plan view and a sectional view showing an embodiment of the present invention.
第1図(a)、(b)に示すように、アイランド3はア
イランド3の4つのコーナーを4本の吊りリート4でリ
ードフレーム外枠11に連結され、また、内部リード5
の延長の外部リード6はタイバー7によって接続され、
リードフレーム外枠11に連結されている。内部リード
5の先端部はアイランド3の周囲に位置し、中央部に孔
】2を持つ基板2がアイランド3上及び内部リート5の
先端から約2mmまでの先端部上に樹脂等の絶縁物で固
着されている。基板2の材質は通常カラスエポキシであ
るため、基板2の下面と内部リード5間の絶縁は保たれ
る。基板2上のプリント配線8は基板2の中央部から放
射状に基板2の外周部に向かいかつ、各々のプリント配
線8に対応する内部リード5に向かって配置されている
。つまり、基板2のプリント配線8と内部り−1・5が
外側ボンディング線10で接続しやすいようにするなめ
である。アイランド3の中央部には半導体ペレッIへ1
か搭載され、半導体ペレット1と外部リード6とは、内
側ボンディング線つとプリント配線8と外側ボンディン
グ線10とで接続されている。As shown in FIGS. 1(a) and 1(b), the island 3 is connected to the lead frame outer frame 11 by four hanging reats 4 at the four corners of the island 3, and also has internal leads 5.
The external lead 6 of the extension is connected by a tie bar 7,
It is connected to the lead frame outer frame 11. The tip of the internal lead 5 is located around the island 3, and a substrate 2 having a hole 2 in the center is coated with an insulating material such as resin on the island 3 and on the tip up to about 2 mm from the tip of the internal lead 5. It is fixed. Since the material of the substrate 2 is usually glass epoxy, insulation between the lower surface of the substrate 2 and the internal leads 5 is maintained. The printed wirings 8 on the board 2 are arranged radially from the center of the board 2 toward the outer periphery of the board 2 and toward the internal leads 5 corresponding to each printed wiring 8. In other words, this is to facilitate the connection between the printed wiring 8 of the board 2 and the inner wires 1 and 5 using the outer bonding wire 10. In the center of island 3, there is a semiconductor pellet I.
The semiconductor pellet 1 and the external lead 6 are connected by an inner bonding wire, a printed wiring 8, and an outer bonding wire 10.
第2図は本発明の第2の実施例を示す断面図である。FIG. 2 is a sectional view showing a second embodiment of the invention.
第3図に示すように、絶縁基板14は、基板2の外径と
ほぼ同じであり、基板2の下面にアイランド3と内部り
−1〈5の先端部を介して、樹脂等の絶縁物で固着され
ている。As shown in FIG. 3, the insulating substrate 14 has approximately the same outer diameter as the substrate 2, and an insulating material such as resin is attached to the bottom surface of the substrate 2 via the island 3 and the tip of the inner wall. It is fixed in place.
この実施例では内部リード5の先端部を基板2に固着す
る接着剤の内部リード5の下面へのはみ出しに影響され
なく、基板2及び゛内部リード5のボンディング部への
熱伝導性が良くなりボンディング性を向上できるという
利点がある。In this embodiment, the adhesive that fixes the tip of the internal lead 5 to the substrate 2 is not affected by the protrusion of the adhesive onto the bottom surface of the internal lead 5, and the thermal conductivity to the bonding portion of the internal lead 5 and the substrate 2 is improved. This has the advantage of improving bonding properties.
以上説明したように本発明は、内部リードを基板外周部
下面に固定することにより、基板の安定性が向上するた
め、樹脂封止時の溶融樹脂の外力による基板の叩きが防
止され、さらにボンディング線の変形や断線を防止てき
る効果がある。よって、ボンディング線の樹脂表面及び
アイランドの樹脂下面への露出もなくなり、組立歩留り
、及びf3 軸性を向上させるという効果を有する。As explained above, the present invention improves the stability of the substrate by fixing the internal leads to the lower surface of the outer periphery of the substrate, thereby preventing the substrate from being hit by external force of the molten resin during resin sealing, and further improving bonding. This has the effect of preventing wire deformation and wire breakage. Therefore, the bonding wire is no longer exposed to the resin surface and the island is not exposed to the resin lower surface, which has the effect of improving assembly yield and f3 axis property.
図面のfffl単な説明
第1[J (a)、(b)は本発明の第1の実施例を示
す一部切欠平面図及び断面図、第2図は本発明の第2の
実施例を示す断面図、第3図(a)。fffl Brief Description of the Drawings 1st [J (a) and (b) are partially cutaway plan views and sectional views showing the first embodiment of the present invention, and Figure 2 is a partially cutaway plan view and sectional view showing the second embodiment of the present invention. A sectional view shown in FIG. 3(a).
(b)は従来の樹脂封止型半導体装置の一例な示す一部
切欠平面図及び断面図である。(b) is a partially cutaway plan view and a sectional view showing an example of a conventional resin-sealed semiconductor device.
1・・半導体ペレッj〜、2・・・基板、3 ・アイラ
ンド、4・・・吊りリード、5・・・内部リート、6・
・・外部リート、7・・・タイバー、8・・・プリント
配線、9・・・内(則ボンディング線、10・・・外(
則ホンディング線、11 ・リードフレーム外枠、12
・・・孔、13・樹脂封止部、14・・・絶縁基板。1...Semiconductor pellet j~, 2...Substrate, 3...Island, 4...Hanging lead, 5...Internal lead, 6...
...External lead, 7...Tie bar, 8...Printed wiring, 9...Inner (regular bonding wire), 10...Outer (
Standard honding line, 11 ・Lead frame outer frame, 12
. . . Hole, 13. Resin sealing portion, 14. Insulating substrate.
Claims (1)
アイランドの周囲に配列して設けた内部リードと、中央
部に前記半導体ペレットの外形より僅かに大きい孔を有
して前記アイランドの周縁部及び前記内部リードの先端
部を接着して固定し且つ表面に配線を有する絶縁性基板
と、前記半導体ペレットと前記配線との間を接続する内
側ボンディング線と、前記配線と前記内部リードとの間
を接続する外側ボンディング線とを有することを特徴と
する樹脂封止型半導体装置。an island on which a semiconductor pellet is mounted in the center, internal leads arranged around the island, and a hole slightly larger than the outer diameter of the semiconductor pellet in the center, and a peripheral portion of the island and the inside. an insulating substrate on which the tip of the lead is bonded and fixed and has a wiring on its surface; an inner bonding wire that connects the semiconductor pellet and the wiring; and a connection between the wiring and the internal lead. 1. A resin-sealed semiconductor device comprising an outer bonding line.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1129162A JPH02307253A (en) | 1989-05-22 | 1989-05-22 | Resin-sealed semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1129162A JPH02307253A (en) | 1989-05-22 | 1989-05-22 | Resin-sealed semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02307253A true JPH02307253A (en) | 1990-12-20 |
Family
ID=15002679
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1129162A Pending JPH02307253A (en) | 1989-05-22 | 1989-05-22 | Resin-sealed semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02307253A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04239161A (en) * | 1991-01-11 | 1992-08-27 | Nec Corp | Resin-sealed type semiconductor device |
| JP2009177123A (en) * | 2008-01-28 | 2009-08-06 | Orient Semiconductor Electronics Ltd | Stacked chip package structure and manufacturing method thereof |
-
1989
- 1989-05-22 JP JP1129162A patent/JPH02307253A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04239161A (en) * | 1991-01-11 | 1992-08-27 | Nec Corp | Resin-sealed type semiconductor device |
| JP2009177123A (en) * | 2008-01-28 | 2009-08-06 | Orient Semiconductor Electronics Ltd | Stacked chip package structure and manufacturing method thereof |
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