JPH0242435U - - Google Patents
Info
- Publication number
- JPH0242435U JPH0242435U JP12237488U JP12237488U JPH0242435U JP H0242435 U JPH0242435 U JP H0242435U JP 12237488 U JP12237488 U JP 12237488U JP 12237488 U JP12237488 U JP 12237488U JP H0242435 U JPH0242435 U JP H0242435U
- Authority
- JP
- Japan
- Prior art keywords
- probe card
- semiconductor device
- substrate
- wiring pattern
- bump electrodes
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000523 sample Substances 0.000 claims description 12
- 239000000758 substrate Substances 0.000 claims description 5
- 239000004065 semiconductor Substances 0.000 claims description 3
- 239000011521 glass Substances 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 4
- 238000007689 inspection Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
Landscapes
- Measuring Leads Or Probes (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Description
第１図は本考案の実施例を示すプローブカード
の断面図、第２図は従来のプローブカードの断面
図、第３図は第２図のプローブカードを用いた検
査方法を示す図、第４図ａ，ｂは第２図のプロー
ブカードの問題点を示す図、第５図ａ，ｂは第１
図のプローブカードを用いた検査方法を示す図、
第６図は本考案の他の実施例を示すプローブカー
ドの断面図、及び第７図は第６図のプローブカー
ドの検査対象となるウエハを示す図である。
１１……ガラス基板（基板）、１２……配線パ
ターン、１６……半導体装置、１８……バンプ電
極、１９……絶縁層。
FIG. 1 is a sectional view of a probe card showing an embodiment of the present invention, FIG. 2 is a sectional view of a conventional probe card, FIG. 3 is a diagram showing an inspection method using the probe card of FIG. 2, and FIG. Figures a and b are diagrams showing problems with the probe card in Figure 2, and Figures a and b are diagrams showing the problems with the probe card in Figure 2.
A diagram showing an inspection method using the probe card shown in the figure.
FIG. 6 is a sectional view of a probe card showing another embodiment of the present invention, and FIG. 7 is a view showing a wafer to be inspected by the probe card of FIG. 6. DESCRIPTION OF SYMBOLS 11... Glass substrate (substrate), 12... Wiring pattern, 16... Semiconductor device, 18... Bump electrode, 19... Insulating layer.
Claims (1)
極と接触させて該半導体装置の電気特性を検査す
るためのプローブカードにおいて、 光透過性の基板の一主面上に、前記バンプ電極
と接触可能な配線パターンを形成したことを特徴
とするプローブカード。 ２ 請求項１記載のプローブカードにおいて、 前記基板をガラス基板で形成し、かつ前記配線
パターンにおけるバンプ電極との非接触箇所を、
絶縁層で被覆したプローブカード。[Claims for Utility Model Registration] 1. In a probe card for testing the electrical characteristics of a semiconductor device by contacting with a plurality of bump electrodes formed on the semiconductor device, on one principal surface of a light-transmitting substrate. A probe card characterized in that a wiring pattern that can be contacted with the bump electrode is formed. 2. The probe card according to claim 1, wherein the substrate is formed of a glass substrate, and non-contact portions with bump electrodes in the wiring pattern,
Probe card coated with an insulating layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12237488U JPH0242435U (en) | 1988-09-19 | 1988-09-19 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12237488U JPH0242435U (en) | 1988-09-19 | 1988-09-19 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0242435U true JPH0242435U (en) | 1990-03-23 |
Family
ID=31370246
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12237488U Pending JPH0242435U (en) | 1988-09-19 | 1988-09-19 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0242435U (en) |
-
1988
- 1988-09-19 JP JP12237488U patent/JPH0242435U/ja active Pending
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