JPH0249670B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an inspection device for a semiconductor test device for confirming the normal operation of a test device for testing a semiconductor device.

[Prior art]

A conventional device of this type is shown in FIG. In the figure, 1 is the main body of the test device, 2 is the semiconductor device to be tested (hereinafter referred to as the semiconductor device under test), 3 is a driver for applying test pulses, and 4 is the output of the semiconductor device under test 2. A comparator for comparing with values obtained at each time point when the test equipment performs a programmed operation; 5 is a pin electronics card equipped with a driver 3 and a comparator 4; 6 is a DC characteristic of the semiconductor device under test 2; 5b is the outlet of the pin electronics card 5 which is the outlet of the test device 1; 7 is a signal line for electrically connecting the pin electronics card 5 and the semiconductor device under test 2; It is. 3a, 4a, 5
a and 6a are driver 3, comparator 4, pin electronics card 5 and DC
This is a relay for connecting/disconnecting the measuring device 6.
2a is an input/output pin (input/output pad) for input/output signals of the semiconductor device under test 2. As shown in FIG.

Next, the operation will be explained. When confirming the functions that the test apparatus 1 should have during the inspection of the semiconductor device under test 2, it is necessary to confirm that the driver 3, comparator 4, and DC measuring instrument 6 of the test apparatus 1 operate normally. The normal operation of each part is confirmed as follows.

During testing, the test apparatus 1 is connected to the input/output pin 2a of the semiconductor device under test 2 for input/output signals via the output 5b of the pin electronics card 5 of the test apparatus 1 and through the signal line 7.

Therefore, first, the semiconductor device under test 2 is transferred to the test equipment 1.
Open relay 5a to disconnect from driver 3 and comparator 4.
a, and the test apparatus 1 is activated so that the driver 3 applies a pulse. If the driver 3 is normal at this time, the applied pulse will reach the comparator 4 on the same pin electronics card 5, and the comparator 4 will check whether the arrived pulse is the same as the one applied by the driver 3. This makes it possible to confirm the normal operation of the driver 3 and comparator 4. In addition, in order to confirm the normal operation of the DC measuring device 6, the relay 6a of the DC measuring device 6 and the relay 3a of the driver 3 are closed, a potential is applied by the driver 3, and the potential is applied by the DC measuring device 6. The DC measuring device 6 by measuring
Normal operation can be confirmed.

In this way, in the conventional device, the semiconductor device under test 2
Since the test device 1 itself was inspected as described above during the test, the function test of the test device 1 itself can be easily realized.

However, in such a conventional method, since the relay 5a of the pin electronics card 5 is opened and the semiconductor test equipment 1 and the semiconductor device under test 2 are separated, the relay 5a and the input/output pin of the semiconductor device under test 2 are connected. 2a, that is, a defect in the test apparatus 1 including the signal line 7, the substrate on which the semiconductor device under test 2 is mounted, etc., cannot be detected.

Therefore, in order to detect defects including the transmission system, a test probe of another measuring device such as an oscilloscope is applied to the input/output pin 2a, and the signal waveform output from the test device 1 is measured. Through observation, normal operation of the transmission system was confirmed.

However, in recent years, as semiconductor devices have become more integrated and the number of input/output pins has increased, test equipment 1
The electrical connection from the exit of the device to the input/output pin of the semiconductor device 2 is crowded, and it is impossible to apply the test probe to the input/output pin position of the device under test. It becomes difficult to confirm that the pulses are being applied correctly. Therefore, with the conventional method as described above, it is impossible to check the functionality of the test apparatus at the input/output pin positions of the semiconductor device under test 2.

[Summary of the invention]

The present invention has been made in view of the above points, and is intended to be applied to a semiconductor device for testing that has the same layout as the input/output pins and power supply pins of the semiconductor device under test and has a simple logic circuit configuration of about one or two gates. By using it instead of a test semiconductor device, applying a test signal generated from the semiconductor test device to the test semiconductor device, and determining the signal from the test semiconductor device to detect whether or not there is a defect in the test device. It is an object of the present invention to provide an inspection device for a semiconductor test device that is capable of confirming the functions of the entire test device including the signal line from the exit of the test device to the inlet of the semiconductor device under test.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. In FIG. 2, numeral 21 is a test semiconductor device having the same input/output signal pin arrangement as the semiconductor device under test, and 21a, 21b, and 21c are input/output pins of the test semiconductor device 21, that is, input/output pads. be. Reference numerals 22, 22a, and 22b are first and second NOR circuits and an inverter that are incorporated into the testing semiconductor device 21 and constitute a logic circuit for testing the functionality of the testing device 1. Further, 5c and 5f are pin electronics cards in the test device 1, and usually a plurality of cards are prepared in the test device 1. 3b and 3d are drivers (inspection signal generation means), 4b and 4d are comparators (judgment means), and 6
are DC measuring instruments, 3c, 3e, 4c, 4e, 5d,
5g, 6b, and 6c are relays. 5e, 5
h are pin electronics cards 5c,
5f, and 7a and 7b are signal lines for providing electrical continuity between the exits 5e and 5h, respectively, and the input/output pads 21b and 21c of the semiconductor device 21 for inspection.

Next, the operation for confirming the normal operation of the test apparatus 1, that is, the normal operation of the driver 3, comparator 4, and DC measuring device 6 using the semiconductor device for inspection 21 will be described. When checking the functions of drivers 3, 3b and comparator 4d, first check each relay 3.
Connect a, 5a, 3c, 5d, 4e, and 5g, apply a pulse from driver 3 and a "LOW" level electric signal from driver 3b, and transmit the inverted waveform of the pulse applied from driver 3 to comparator 4d. Check whether it was done. If the inverted waveform is confirmed, the relays 3a and 5 are transferred from the driver 3.
It can be confirmed that the signal line a and the signal line 7 are operating normally, and that the signal line 7b, the contact 5h, the relays 5g and 4e, and the comparator 4d are operating normally. That is, it is possible to confirm the normal operation of the test apparatus 1 at the input/output signal pads of the semiconductor device under test.

Further, the normal operation of the DC measuring device 6 is confirmed as follows. First, each relay 3c, 5d, 3
e and 5g are connected, and the input/output pad 21a of the semiconductor device for inspection 21 is kept at a specific potential using the drivers 3b and 3d. That is, by applying a "HIGH" level potential to the driver 3b and a "LOW" level potential to the driver 3d, a "HIGH" level potential is obtained at the input/output pad 21a. This potential
DC by measuring through the DC measuring device 6, relays 6a, 5a, contacts 5b and signal line 7.
It is possible to confirm the normal operation of the testing semiconductor device 21 of the measuring instrument system up to the input/output pad 21a.

By applying the above procedure to each driver and comparator, it is possible to confirm the normal operation of the test equipment at each input/output pad.

Furthermore, an appropriate program is installed in the CPU of the test device 1, and each of the above drivers, comparators,
By sequentially operating each relay, it is possible to detect a defective location in the test equipment including the transmission system from each result, and display the results on a display means such as a CRT installed in the test equipment 1. You can easily find its location by displaying it on the screen.

According to the apparatus of this embodiment, the test semiconductor device 21 having input/output pins and power supply pins arranged in the same manner as the semiconductor device under test is used instead of the semiconductor device under test.
, the test signal from the test device 1 is applied to the test semiconductor device 21, and the operation of the test device 1 is confirmed by determining the signal from the device 21. Semiconductor device 2
To easily confirm the normal operation of the entire test equipment including the transmission system from the exit of the test equipment 1 to the entrance of the semiconductor device under test even when the test equipment is integrated and has a very large number of input/output pins. be able to.

Furthermore, if the semiconductor device under test 2 has a small number of input/output pins, conventionally, problems in the transmission system from the exit of the test device 1 to the entrance of the semiconductor device under test have been confirmed using an oscilloscope or the like. In this method, an inspection probe such as an oscilloscope is connected to the input/output pads of the semiconductor device under test, and the operation is checked under conditions that are slightly different from the actual test conditions. In contrast, in this embodiment, the operation of the entire test apparatus including the transmission system can be checked under conditions exactly similar to the actual test conditions, and the test results are more reliable.

Here, an inspection similar to the above embodiment can be performed using an actual semiconductor device under test, but when performing an inspection using this semiconductor device under test, even if there is a defective part, Even if it is determined that the internal logic circuit of the semiconductor device under test is generally very complex, it is often unclear whether there is a defect in the test apparatus 1 or the semiconductor device under test. On the other hand, in the apparatus of this embodiment, a test semiconductor device 21 consisting of a very simple logic circuit is used instead of the semiconductor device under test, so that defective parts of the test apparatus 1 can be easily identified.

In the above embodiment, the test semiconductor device includes simple logic, but the device may not include a logic gate and a simple resistor may be built into the device, as shown in FIG.

〔Effect of the invention〕

As described above, according to the present invention, a test semiconductor device consisting of a simple logic circuit having the same input/output pin arrangement as the semiconductor device under test is used, and a test signal generated from the test device is used for this test. Since we decided to detect whether there is a defect in the test equipment by judging the signal sent to the semiconductor device and from the device, we included the transmission system from the exit of the test equipment to the input/output pin entrance of the semiconductor device under test. This has the effect of allowing you to easily check the functionality of the entire test equipment.

[Brief explanation of drawings]

Figure 1 is a block diagram of a conventional semiconductor test equipment.
FIG. 2 is a block diagram of a testing device for a semiconductor testing device according to an embodiment of the present invention, and FIG. 3 is a diagram showing an example in which the internal logic of a semiconductor device for testing is changed in the device. 1... Semiconductor test equipment, 2... Semiconductor device under test,
3, 3b, 3d...driver (inspection signal generation means), 4, 4b, 4d...comparator (judgment means), 5, 5c, 5f...pin electronics card, 6...DC measuring device, 21, 31...inspection semiconductor Devices 22, 22a, 22b...gates forming a logic circuit. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

[Scope of Claims] 1. An inspection device for a semiconductor test device for testing a semiconductor test device including a transmission system from an outlet of the test device to each input/output pin and power supply pin of a semiconductor device under test, comprising: A semiconductor device for testing, which has input/output pins and power supply pins arranged in the same manner as the semiconductor device under test, and a circuit that allows electrical signals to be transmitted bidirectionally between the input/output pins, and a circuit installed in a semiconductor testing device. and a test signal generating means for generating a test signal and applying it to any of the input/output pins of the semiconductor device for test via a signal line, and from any of the input/output pins of the semiconductor device for test. A determination means for receiving the output test signal and determining the presence or absence of an abnormality in the same transmission path as the transmission system of the test signal to the input/output pin and power supply pin of the semiconductor device under test. Inspection equipment for semiconductor testing equipment featuring features. 2. The above semiconductor testing device includes a plurality of cards each equipped with the above-mentioned test signal generation means and judgment means, and sequentially operates the plurality of test signal generation means and judgment means, and identifies a defective location from each result. 2. An inspection device for a semiconductor testing device according to claim 1, comprising: a CPU for detecting a defect; and a display means for displaying a defective location detected by the CPU.