JPH0258335A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To shorten manufacturing steps, to reduce the area of a junction and to decrease a parasitic capacity by forming a P-type buried layer and an N-type buried layer with one mask in a self-alignment manner to isolate elements, and employing both a selective epitaxial growth and a polysilicon growth. CONSTITUTION:After N-type impurity is diffused on the surface of a P-type Si substrate 101, the substrate 101 except a part to become a collector region removed, and a mesalike high concentration N-type diffused layer 102 is formed. An SiO2 film 103 and an Si3N4 film 104 are formed on the surface. The films 103, 104 on the parts except the side faces of the layer 102 are removed, and a BSG layer 105 is grown on the periphery. Then, it is heat treated to form a high concentration p-type diffused layer 106 as an element isolation region. That is, the layer 102 as the N-type buried layer and the layer 106 as the P-type buried layer are formed of one mask in a self-alignment manner.

Description

DETAILED DESCRIPTION OF THE INVENTION [Already Required] The present invention aims to reduce parasitic capacitance by shortening the manufacturing process and reducing the junction area in a method of manufacturing a high-speed bipolar transistor.

After forming a mesa-shaped high-concentration N-type diffusion layer on the surface of the P-type Si substrate and growing BSfJ around it, heat treatment is performed to diffuse P-type impurities from the 850 layer to form element 11. By combining the process of forming a high-concentration P-type diffusion layer as a region, one-selective epitaxial growth, and polynolycon growth, it is possible to form a collector region of a rectangular product, a collector lead-out wiring of a boronoricon, a base region of a single crystal, and a polynolycon. After forming 11117 base lead wirings, growing a 5i02 film on one surface, opening the part where the emitter is to be formed on the base region, and growing an N-type polynolycon layer, then
The method is structured to include a step of diffusing type impurities to form an emitter region.

[Industrial 111 Layer Field] The present invention relates to a method of manufacturing a semiconductor device, particularly a method of manufacturing a high speed bipolar transistor.

In recent years, with the demand for higher speed bipolar transistors, there has been a demand for miniaturization of elements and reduction of parasitic elements, especially parasitic capacitance.

For this reason, various types of base-emitter self-line technologies have been provided, but it is necessary to further consider reducing the junction area.

[Conventional technology]

FIG. 7 is a diagram showing an example of a bipolar transistor using conventional base-emitter self-line technology.

In No. 711ia, 301 is a P-type Si substrate, 302
303 is the N-type buried layer with a high 7 dia for collector extraction; 303 is the N-type Ebitaki soyal layer that constitutes the collector region; 304
305 is a base region, 306 is a base-drawing polysilicon 15, 307 is a Sin film, 30
8 is a SiO2 film, 309 is an N-type polysilicon layer, 310
is an emitter region, 311 is an emitter electrode wiring, 312 is a base electrode wiring, and 313 is a collector electrode wiring.

Below, using Figure 7, we will explain how to construct a bipolar transistor using the conventional base-emitter self-line technology!
! ! I will explain how to make it.

(2) P-type 5i) N-type impurities such as P and ^S are introduced into the surface of the L plate 301 by diffusion or ion implantation to form a high concentration N-type buried layer 302. This height); degree N type buried layer 30
2 is used to pull out the collector to the outside.

■N-type epitaxial layer 30 on the surface of the 5iJJ board 301
Grow 3. This N-type epitaxial layer 303 is
Configure the collector area. At this time, at the same time, a highly doped N-type buried layer 302 and a collector electrode wiring 313 to be formed later are formed.
A highly doped N-type epitaxial layer is also formed to provide electrical conduction.

■After patterning N-type epitaxial N303,
A Sin film 304 is grown by CVD or the like.

(2) A P-type base region 305 is formed by introducing a P-type impurity such as B into the surface of the N-type epitaxial layer 303 by expansion 11 or ion implantation.

2) Grow Si on &I7j to form a base-extracting polysilicon layer 30G.

@ After growing a SiOz film 307.308 on the surface by CVD method etc., RIE (reactive ion process 7)
A portion of the S10□■'A 308 where the emitter is to be formed is opened by etching or the like, and the surface of this opening is oxidized to form a thin 5i02 film.

After growing polysilicon on the 0 surface, an N-type polysilicon layer 309 is formed by ion-implanting As or the like. Thereafter, by heat treatment, the A in the N-type polysilicon layer 309 is
s is diffused into the surface of the base region 305 to form an emitter region 310.

■ Emitter electrode wiring is formed by depositing N on the surface of the N-type borin silicon layer 309, and the SO□ film 30
A base electrode wiring 312 is formed by opening a predetermined portion of the Si0□ film 307 and depositing N, and a collector electrode wiring 313 is formed by opening a predetermined portion of the Si0□ film 307 and depositing N. .

By going through the above steps, a bipolar transistor is completed.

Although omitted in the above description, in the case of the conventional bipolar transistor shown in FIG. 7, it is necessary to perform element isolation. For element isolation, in addition to (1) the high-concentration N-type buried layer 302, a 1) type buried layer for element isolation is formed under the 5iO1 film 304; ■Dig a trench around the element. ■ Perform selective oxidation.

[Problem to be solved by the invention]

In element isolation of conventional bipolar transistors
l) When using an N-junction, it is necessary to provide a certain distance between the 1) type diffusion layer and the N-type diffusion layer so that the withstand pressure in the feeding force direction does not deteriorate; There is a problem in that it is necessary to use a mask, and when a trench is used, there is a problem in that it is necessary to go through multiple enoting and oxidation steps.Furthermore, in the case of one selective oxidation, 5i) Put stress on the fE plate, Sii
However, there was a problem in that crystal transition occurred.

In the present invention, a P-type buried layer and an N-type buried layer are formed in the self-line with one mask to isolate the elements, and the collector region and the /<-- An object of the present invention is to provide a method for manufacturing a semiconductor device, in particular a method for manufacturing a bipolar transistor, in which the manufacturing process is shortened and the junction area is reduced by forming a space region to reduce parasitic chambers.

(Means for Solving the Problems) In order to achieve the above object, a method for manufacturing a semiconductor device, particularly a method for manufacturing a bipolar transistor, according to the present invention, comprises:
After diffusing N-type impurities on the surface of the P-type Si substrate, unnecessary portions of the Si material are removed by patterning to form a mesa-shaped high-concentration N-type diffusion layer; 1. Type diffusion layer. After growing a BSG layer around the 'il, heat treatment is performed to diffuse P type impurities from the BSG layer to form a high concentration P type diffusion layer as the element bone H region. After the growth, a collector made of single-crystal Si is formed on the highly concentrated N-type diffusion layer by opening the part where the collector is to be formed on the highly concentrated N-type diffusion layer, and growing Si on the surface. After forming a region and forming an N-type polycone layer as a collector lead wiring on the SiO□ layer and growing an SiO□ film on one surface,
The part on the collector region where the base is to be formed is opened and Si is grown on the surface.

A base region made of sentinel Si is formed on the collector region, and a P-type polysilicon layer as a base lead wiring is formed on the SiO□ film.
After growing the film, there is a step of opening the part on the base region where the emitter is to be formed, and after growing the N-type polycone layer, the emitter 6R region is formed by diffusing N-type impurities into the base region. The process consists of the following steps:

FIG. 1 is a diagram explaining the principle of the present invention.

In Fig. 1, 101 is 51 substrate, ]02 is high, ;N type diffusion layer, 103 is SiO□ film, +04 is Si3N4
105 is a BSG layer, 106 is a high concentration N-type diffusion layer, 1
07 is S10. 108 is a collector region 109 is an N-type polysilicon layer, 110 is a 5iO7 film Ill is a base region, 112 is a P-type 7 (ξ relay 932 layer, 113 is a 5i0
2, 114 is an N-type polysilicon layer, 115 is an emitter region, 116 is an emitter electrode wiring, 117 is a base electrode wiring, and 118 is a collector electrode wiring.

[Effect]

1. A method for manufacturing a semiconductor device according to the present invention, using FIG.
In particular, with one mask, a P-type buried layer and an N-type buried layer are added to the self-line.
A mold buried layer is formed to perform element isolation, and a collector region and a base region are formed by using iZ selective epitaxial growth and polysilicon growth in combination. A method of manufacturing a bipolar transistor will be explained.

Element separation according to the present invention is performed by the following injections.

■P-type 5i) After diffusing N-type impurities on the surface of the fE plate 101, the Sil temporary +
01 is removed to form a mesa-shaped heavily doped N-type diffusion layer 102.

A SiO□ film 103 and a Si, N, film 104 are formed on the 0 surface.

(2) The 5i02 film and the 5iJ- film are removed from the portions other than the side surfaces of the mesa-shaped high concentration N-type diffusion layer 102.

(2) Mesa-shaped chamber: A BSG layer +05 is grown around the N-type diffusion layer 102.

(2) A heat treatment is performed to diffuse B from the 850 layer 105 into the Si substrate 101 to form a high concentration N-type diffusion layer 106 as an element isolation region.

According to the method for forming element isolation of the present invention, the high concentration N-type diffusion layer 102 is used as the N-type buried layer which is the base for forming the bipolar transistor body, and the P-type buried layer 102 is used as the P-type buried layer forming the element isolation region. The high concentration P-type diffusion layer 106 can be formed in the self-line with one mask.

Further, the formation of the bipolar transistor main body of the present invention is performed by the following method +111.

(2) After growing the SiJ film +07 on the surface of the SiW plate 101 on which the high concentration P type diffusion layer 106 has been formed and performing element isolation, the portion of the high concentration N type diffusion layer 1021 where the collector is to be formed is opened.

0 surface to form a collector region 108 made of single crystal Si on the high concentration N type diffusion layer 102,
On the 5inf film 107, an N-type polysilicon layer 109 is formed as a collector lead-out wiring.

After growing a 5iOz film 110 on the 0 surface, a portion on the collector region 108 where a base is to be formed is opened.

A base region III made of single crystal Si is formed on the collector region 108 by growing Si on the surface of the base region 108.
A P-type polysilicon layer 112 is formed on the O□ film 11 as a 10 base lead-out wiring.

After growing a 5iOz film 113 on the 0 surface, a portion on the base head region Ill where an emitter is to be formed is opened.

■After growing the N-type borin silicon layer 114.

An emitter region 115 is formed by diffusing N-type impurities into the base region 111.

Since the bipolar transistor body of the present invention is formed in a hierarchical manner using a combination of one-selective epitaph growth and polysilicon growth, the junction area can be reduced and, therefore, the parasitic capacitance can be reduced.

[Husband example]

FIGS. 2 to 6 are diagrams showing each process of an embodiment of the present invention.

In FIGS. 2 to 6, 201 is a P-type S1 substrate.

202 HaAC degree N type diffusion N, 203 Ha5iOz
llQ, 204 is SiO□ film, 205 is 5isN4
206 is a BSG layer, 207 is a high 1 concentration P type diffusion layer 9
208 is a SiO□ film, 209 is a collector region, 21O is an N-type polysilicon layer, 211 is S+0. 212 is the base region of the membrane.

213 is a P-type polysilicon layer, and 214 is a 5i02 film.

215 is an N-type borin silicon [, 2+6 is an emitter region,
2I7 is the emitter N, pole wiring, 218 is the base electrode wiring, and 219 is the collector electrode wiring.

Hereinafter, each process of one embodiment of the present invention will be explained using FIGS. 2 to 6.

(Step 1. See FIG. 2) N-type impurities such as As and P are diffused over the entire surface of the P-type S1 substrate 201 to form a high concentration N-type diffusion layer 202.

Next, S10□11 layer 203 is thermally grown to a thickness of about 1000 mm.

Part 7.1. The Si substrate 201 is patterned by etching to form a mesa-shaped heavily doped N-type diffusion layer 202.

This mesa-shaped high concentration N-type diffusion layer 202 is a bipolar
This serves as the base for forming the transistor body.

And 1 surface has a thickness of about 1000 people; ozll mulberry 20
4 was thermally grown to a thickness of 70 mm using the CVD method.
Form 5izN4 crotches 205 for 0 to 1000 people.

(Step 2, see FIG. 3) Etching such as RIE is performed on the entire surface, leaving the SiO□ film 204 and the 5iJa film 205 only on the side walls of the mesa-shaped high concentration N type diffusion layer 202.

Next, QBSG is grown on one surface by the CVD method, reflowed, and then flattened by etch hacking to form BS (4206).

Thereafter, heat treatment is performed to diffuse B from the BSG layer 206 into the Si substrate 201 to form a high concentration P-type diffusion layer 207. This high concentration N type diffusion layer 207 is the BSG layer 20
6 functions as an element isolation region.

(Process 3. See Figure 4) A SiO
After growing to a thickness of zero, the SiO□ films 203 and 208 on the high concentration N-type diffusion layer 202 are patterned.

Next, Si is grown on the entire surface. As a result, high concentration of N
A structural crystal 5i grows on the type diffusion layer 202 to form a collector region 209. In addition, silicon was grown on the SiO□ film 20, and N was used as the collector lead wiring.
A mold wheel 9 flexible container layer 210 is formed. Unnecessary portions of the N-type car 9 freecon layer 210 are patterned.
Remove.

After that, the 5i02 film 21 is deposited on the entire surface using the CVD method.
1 to a thickness of 3,000 to 4,000 people.

(Step 4. See FIG. 5) After opening is formed in the portion of the SiO7 film 211 where the base is to be formed by patterning, a film 31 is grown on the entire surface. As a result, single crystal Si grows on the collector region 209 and forms the base region 212. Also.

Silicon is grown on the SiO□ film 21 to form a P-type polysilicon layer 213 as a base lead wiring. The unnecessary part of P type polysilicon @213 is
Perform patterning and remove.

After that, three S10□ films 2+4 were applied to the entire surface by CVD method.
Formed to a thickness of 000 to 4000 people.

(Step 5. See Figure 6) After opening the part where the emitter of SIOzBQ 214 is to be formed by patterning, non-doped polysilicon is grown by CVD method, and N-type impurities such as 8S and p are ion-implanted into this. After introducing the polysilicon layer 215, unnecessary portions are removed by patterning to form an N-type polysilicon layer 215.

Next, heat treatment is performed to diffuse the N-type impurity in the N-type polysilicon store 215 into the surface of the base region 212 to form an emitter region 216.

After depositing A1 on the second layer, patterning is performed to form an emitter electrode wiring 217. Base electrode wiring 21
8 and collector electrode wiring 219 are formed.

Through the above steps, the bipolar transistor of the present invention is completed.

〔Effect of the invention〕

According to the present invention, with one mask, it is possible to form an N-type buried layer that serves as a base for forming a bipolar transistor body in a self-line, and a P-type buried layer that serves as an element isolation region. At the same time, the BSG layer, which is a diffusion source for forming the P-type buried layer, can be used as is for device separation, which shortens the manufacturing process compared to conventional selective oxidation or trench-based device separation. You can do it for 11 hours.

In addition, since the bipolar transistor body is formed hierarchically using a combination of selective IR epitaxial growth and polysilicon growth, the junction area is smaller than that of a bipolar transistor formed using conventional base-emitter self-line technology. can be reduced.

As a result, the parasitic capacitance is reduced and the performance of the bipolar transistor is improved.

[Brief explanation of the drawing]

FIG. 1 is a diagram explaining the principle of the present invention. FIG. 2 to FIG. 6 are diagrams showing each process of one embodiment of the present invention. FIG. 7 is a diagram showing a conventional example. In Figure 1 101: Si substrate 102: High concentration N type diffusion layer +03:SiO□ film 104: sl, N4 membrane 105:850 layer 106: High third base degree P type expansion 18! layer 107:SiO! film 108: Collector area 10.1: N-type polysilicon layer 110: SiO□ film Ill base area 112: P-type polysilicon 113: sio, 1112 114: N-type polysilicon layer 115: Eminota area 116: Eminota electrode wiring 117・Base electrode wiring II8: Collector electrode wiring

Claims (1)

[Claims] After diffusing N-type impurities into the surface of the P-type Si substrate (101), unnecessary portions of the Si substrate (101) are patterned.
1) is removed to form a mesa-shaped high concentration N-type diffusion layer (102).
After growing a BSG layer (105) around the mesa-shaped high concentration N-type diffusion layer (102), heat treatment is performed to form a BSG layer (
105) to form a high concentration P type diffusion layer (106) as an element isolation region, and after growing a SiO_2 film (107) on the surface, a high concentration N type diffusion layer (107) is formed. 102) A step of opening the part where the collector is to be formed on the top, and growing Si on the surface to form a high concentration N-type diffusion layer (102).
A collector region (108) made of single-crystal Si is formed on the top, an N-type polysilicon layer (109) as a collector lead-out wiring is formed on the SiO_2 film (107), and a SiO_2 film (110) is formed on the surface. ) is grown, a step of opening a portion on the collector region (108) where a base is to be formed, and a step of growing Si on the surface and forming a base region (made of single crystal Si) on the collector region (108). 111),
A process of forming a P-type polysilicon layer (112) as a base lead wiring on the SiO_2 film (110), and after growing a SiO_2 film (113) on the surface, forming an emitter on the base region (111). The second step is to form an emitter region (115) by growing an N-type polysilicon layer (114) and then diffusing N-type impurities into the base region (111). A method for manufacturing a semiconductor device.