JPH0260221B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a field effect transistor and an integrated circuit using the same.

[Prior Art] The applicant proposed a field effect transistor having the structure shown in FIG. 1 in Japanese Patent Laid-Open No. 119671/1983. This field effect transistor has a source region 1
, a drain region 2, a channel forming region 3 made of a first semiconductor provided in contact with these source and drain regions 1 and 2, and first and second gates provided on this channel forming region 3. The first gate layer 4 is composed of at least layers 4 and 5 and is in contact with the channel forming region 3.
The second gate layer 5 is made of a material having a lower resistance than the first gate layer 4 or a semiconductor having a higher impurity concentration than the first semiconductor. ing. 6 is an insulating substrate, 7, 7',
7'' is an ohmic electrode, 8 is a source, 9 is a drain, and 10 is a gate.

In this transistor, by using a semiconductor with a low impurity concentration as the second semiconductor constituting the first gate layer 4 which is in contact with the first semiconductor constituting the channel forming region 3, the gate threshold of the field effect transistor can be increased. The value voltage can be made independent of the impurity concentration of the second semiconductor. Depending on the type of field effect transistor, it is possible to design the gate threshold voltage to be given only by the difference in work function between the materials of the first semiconductor of the channel forming region 3 and the materials of the second gate layer 5. , it becomes easier to manufacture field effect transistors with uniform characteristics over a large area, and it becomes easier to realize large-scale integrated circuits. Further, it is possible to avoid deterioration of the characteristics of the field effect transistor due to the influence of interface states between the first semiconductor 3 and the second semiconductor 4, traps, etc., and the influence of carrier freezing at low temperatures. This effect is particularly noticeable when a high-quality MIS type structure is not obtained, such as when the first semiconductor 3 is a compound semiconductor. That is, by applying such a field effect transistor to a compound semiconductor, it is possible to obtain an extremely high speed, low power consumption, homogeneous field effect transistor that takes advantage of the high electron mobility of the compound semiconductor.

[Problems to be Solved by the Invention] Generally, when a field effect transistor is used to construct an electronic circuit, it is desired that the gate threshold voltage of the transistor can be set to any desired value. For example, in a direct-coupled logic circuit using normally-off transistors, the gate threshold voltage of the transistor is approximately 20° below the power supply voltage.
It is recommended to set it to %. However, in the conventional technology, it is not possible to set the gate threshold voltage to an arbitrary desired value, and even in the field effect transistor according to the above-mentioned Japanese Patent Application Laid-Open No. 58-119671, the gate threshold voltage is set to a second value. Although it is possible to make it independent of the impurity concentration of the semiconductor, the gate threshold voltage is still determined by the difference φ between the work function of the first semiconductor of the channel forming region 3 and the work function of the material of the second gate layer 5. It is highly dependent on _GS and cannot be set to any desired value. This study clarifies how to set the parameters arbitrarily and with good controllability.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a field effect transistor according to Japanese Patent Application Laid-open No. 58-119671, in which the gate threshold voltage can be set to any desired value with good controllability. be.

Another object of the present invention is to provide an integrated circuit in which field effect transistors with uniform characteristics are integrated and arranged over a large area, and which consumes less power.

[Means for solving the problem] In order to achieve such an object, the present invention provides a combination of semiconductors in which φ _GS is not zero, that is,
A first semiconductor and a second semiconductor constituting a channel forming region.
The semiconductor of the gate layer is selected to have a different work function.

A first aspect of the present invention includes a source region, a drain region, a channel forming region made of a first semiconductor provided in contact with the source region and the drain region, and a first and second semiconductor provided on the channel forming region. The first gate layer, which is composed of at least a second gate layer and is in contact with the channel forming region, is composed of a second semiconductor having a larger band gap and lower impurity concentration than the first semiconductor; In a field effect transistor made of a material with lower resistance or a semiconductor with a higher impurity concentration than the first semiconductor, the second gate layer is made of a semiconductor having a different work function from the first semiconductor forming the channel forming region. It is characterized by what it did.

A second aspect of the present invention includes a source region, a drain region, a channel forming region made of a first semiconductor provided in contact with the source region and the drain region, and a first and second semiconductor provided on the channel forming region. The first gate layer, which is composed of at least a second gate layer and is in contact with the channel forming region, is composed of a second semiconductor having a larger band gap and lower impurity concentration than the first semiconductor; In a field effect transistor made of a material with lower resistance or a semiconductor having a higher impurity concentration than the first semiconductor, the second gate layer is made of a semiconductor having a different work function from the first semiconductor forming the channel forming region. The present invention is characterized in that a plurality of the above-described field effect transistors are arranged on the same chip.

[Operation] The operation of the present invention will be explained using an example of a field effect transistor whose energy band diagram is shown in FIGS. 2A to 2C. In this transistor, the first semiconductor of the channel forming region 3 is an n-type semiconductor, the second gate layer 5 is an n ⁺ type (n-type high impurity concentration) semiconductor, and the n-channel transistor operates in a charge accumulation mode.
It is a transistor. Further, it is assumed that the thickness t ₂ and the impurity concentration N ₂ of the second semiconductor of the first gate layer 4 are each sufficiently small, and the gate threshold voltage of the transistor is not defined by these values.

Further, in the examples shown in FIGS. 2A to 2C, the work function of the second gate layer 5 is larger than that of the first semiconductor 3. Note that FIG. 2A shows the case where the gate voltage V _G is set so as to satisfy the flat band condition.

When the gate voltage V _G is zero, the band diagram becomes as shown in FIG. Leave. No charges are induced in the channel forming region 3 in contact with the first gate layer 4 . Therefore, this transistor is a so-called normally-off type transistor in which no current flows when the gate voltage V _G is zero.

In order to cause a large amount of current to flow through this transistor, the gate voltage V _G is made positive as shown in FIG. 2C. As a result, the conduction band lower end 11 of the channel forming region 3 is located below the Fermi level 12 for the first time near the first gate layer 4, and a large amount of charge is induced.

Next, the conditions necessary to obtain the band diagrams shown in FIGS. 2A to 2C will be described. The work function difference φ _GS between the first semiconductor 3 and the second gate layer 5 is expressed as follows using the energy level in the flat band state (see FIG. 2A).

φ _GS = ψ _GS − (E _F − E _C ) ₂ + (E _F − E _C ) ₁ Here, ψ _GS is the lower end of the conduction band 11, 1 of each semiconductor.
1′, and (E _F −E _C ) ₂ and (E _F −E _C ) ₁ are the Fermi level E _F and the lower end of the conduction band in the second gate layer 5 and the first semiconductor 3, respectively. It represents the difference between the energy E _C of This energy difference (E _F −E _C ) takes a value determined by the impurity density and effective density of states of the semiconductor, but
For practically useful semiconductors, it is as small as a few millivolts.

Therefore, in order to set the work function difference φ _GS to any desired value, it is only necessary to set ψ _GS to any desired value. On the other hand, since ψ _GS is a material constant determined by the types of semiconductors of the first semiconductor 3 and the second gate layer 5, its value is not influenced by manufacturing conditions and can be set to a desired value with good controllability. Can be done.

In the following description, the channel forming region 3 is
Taking the case of GaAs as an example, in that case, the second gate layer 5 is made of, for example, In _1-x Ga _x As (0≦x≦
By using 1), a band diagram as shown in FIG. 2A can be obtained, and ψ _GS can be arbitrarily set. x=0, that is, second gate layer 5
When is GaAs, ψ _GS =0. When x=1, that is, the second gate layer 5 is InAs, ψ _GS =
It is known to be 0.83eV. 0≦x≦1,
That is, when the second gate layer 5 is an In _x Ga _1-x As mixed crystal, ψ _GS increases as x increases, but by appropriately selecting x, it can be adjusted to 0 and 0.83 eV.
It can take any value between. Therefore, when the channel forming region 3 is made of GaAs,
By using In _1-x Ga _x As as the second gate layer 5 and appropriately selecting its composition ratio x, the gate voltage that brings about the flat band state of the transistor can be approximately set to any value between 0 and 0.83V. Can be set to a value. This voltage is practically equal to the gate threshold voltage.

[Example] The present invention will be described in detail below with reference to the drawings.

The structure of the field effect transistor of the present invention is shown in FIG. 1, and the energy band diagram of one embodiment thereof is shown in FIGS. 3A and 3B. As shown in FIG. 3A, by setting φ _GS <0, this transistor can be made into a normally-on charge storage type. That is, when the gate voltage is zero, as shown in FIG. 3B, the lower end 11 of the conduction band of the first semiconductor 3
is below the Fermi level 12 at the boundary with the second semiconductor 4, and a large amount of accumulated charge can be generated there.

In order to have an energy band diagram as shown in FIG. 3A, when the first semiconductor 3 is GaAs, the second
As the gate layer 5, for example, Al _x Ga _1-x As (0≦x≦
1) may be used.

As shown in Figure 4, the flat band condition
When the first semiconductor 3 is p-type and the semiconductor of the second gate layer 5 is p ⁺ type (p-type high impurity concentration), if φ _GS <0, the transistor is a p-channel normally-off type charge storage. It can be made into a mold. In order to have an energy band diagram as shown in FIG. 4, when the first semiconductor 3 is GaAs, for example, In _x Ga _1-x As (0≦x≦1) is used as the second gate layer 5. good. If ψ _GS represents the energy difference between the upper ends 13 and 13' of the valence bands of the two semiconductors 3 and 5, then x=0, that is, the second gate layer 5
In the case of GaAs, ψ _GS = 0, and x = 1, that is, when the second gate layer 5 is InAs, ψ _GS = -
It is known to be 0.24eV. 0≦x≦1,
In other words, when the second gate layer 5 is a mixed crystal of In _x Ga _1-x As, as x becomes larger, ψ _GS becomes more negative, but by appropriately selecting x, ψ _GS can be reduced to 0.
and -0.24eV can be set to any desired value. In addition, the difference between ψ _GS and the work function difference φ _GS is n
As with other types of semiconductors, the value is determined by the impurity density and effective state density of each semiconductor, but in a practically useful semiconductor it is as small as several milli-eV.
Therefore, when the channel forming region 3 is made of GaAs, by using In _1-x Ga _x As as the second gate layer 5 and appropriately determining the composition ratio x,
The gate voltage that results in a flat band condition of the transistor can be set to any desired value between approximately 0 and -0.24V. This voltage is approximately equal to the gate threshold voltage.

Furthermore, as shown in FIG. 5 in a flat band state, the first semiconductor 3 is p-type and the second gate layer 5
When the semiconductor is p ⁺ type, the transistor can be made into a p-channel normally-on charge storage type by setting φ _GS >0. For this purpose, when the first semiconductor 3 is GaAs, for example, Al _x Ga _1-x As (0≦x≦1) may be used as the second gate layer.

Furthermore, when the first semiconductor of the channel forming region 3 is GaAs, the second gate layer 5 is not necessarily In _x
It is clear that it is not limited to Ga _1-x As and Al _x Ga _1-x As; for example, AlGa _1-x As _y P _1-y (0≦x,
y≦1), Al _x Ga _1-x As _y Sb _1-y (0≦x, y≦1),
In _x Al _y Ga _1-xy As (0≦x, y≦1), In _x Ga _1-x
As _y P _1-y (0≦x, y≦1), or In _x Ga _1-x
It may be configured by As _y S _b1-y (0≦x, y≦1).

Furthermore, it is clear that the first semiconductor of the channel forming region 3 is not necessarily limited to GaAs; for example, InP, In _x Ga _1-x As (0≦x≦1), etc. may be used. In that case, the second gate layer 5 is, for example, In _x Ga _1-x As _y P _1-y (0≦x, y≦1),
Al _x GA _1-x As _y P _1-y (0≦x, y≦1), In _x Al _1-x
As _y P _1-y (0≦x, y≦1) may be used.
Alternatively, In _x GA _1-x Sb (0≦x≦1) can also be used as the first semiconductor of the channel forming region 3 . In that case, the second gate layer 5 may be made of, for example, In _y Ga _1-y Sb (0≦y≦1). Alternatively, Si can be used as the first semiconductor of the channel forming region 3, and in that case, the second semiconductor
As the gate layer 5, for example, Si _x Ge _1-x (0≦x≦
1) may be used.

Furthermore, by fabricating transistors with different materials or impurity types for the second gate layer 5 on the same chip, it is possible to realize a high-performance integrated circuit in which transistors with different gate threshold voltages are combined. For example, by combining Figures 2, 3, and 5, an n-channel normally-off type can be obtained as a switching transistor, and a P-channel or n-channel normally-on type transistor can be used as a load. It is possible to construct integrated circuits such as gates and memories based on so-called E/D type inverters. This makes it possible to realize a low-power, high-speed integrated circuit. Alternatively, by using the combination of FIGS. 2 and 4, it is also possible to obtain a normally-off complementary circuit for both the p-channel and n-channel.

As described above, according to the present invention,
In the field-effect transistor according to No.-119671, the gate threshold of the field-effect transistor is improved by configuring the second layer constituting the gate with a semiconductor having a different work function from the first semiconductor constituting the channel forming region. Since the value voltage can be set arbitrarily and with good controllability, it becomes easy to manufacture field-effect transistors with uniform characteristics over a large area, making it easy to realize large-scale integrated circuits. can.

[Effects of the Invention] As explained above, the transistor according to the present invention makes it possible to easily obtain a large-scale integrated circuit with low power consumption, and contributes to the technical field of high-speed electronic computers and electronic devices for high-speed communication. It is extremely large.

[Brief explanation of drawings]

FIG. 1 is a schematic cross-sectional view showing a configuration common to field effect transistors according to the prior art and the present invention, and FIG.
Figures A to C are energy band diagrams showing the operating principle of the field effect transistor according to the present invention, and Figures 3A, B, 4 and 5 are energy band diagrams of embodiments of the present invention. 1... Source region, 2... Drain region, 3...
...Channel formation region or first semiconductor, 4...
Gate first layer or second semiconductor, 5... Gate second layer, 6... Substrate, 7... Ohmic electrode, 8...
...Source, 9...Drain, 10...Gate, 1
1, 11'...lower end of conduction band, 12,12'...Fermi level, 13,13'...upper end of valence band.

Claims (1)

[Scope of Claims] 1. A source region, a drain region, a channel forming region made of a first semiconductor provided in contact with the source region and the drain region, and a first channel forming region provided on the channel forming region. and a second gate layer, the first gate layer in contact with the channel forming region is made of a second semiconductor having a larger band gap and lower impurity concentration than the first semiconductor, In a field effect transistor, the layer is made of a material having a lower resistance than the first layer or a semiconductor having a higher impurity concentration than the first semiconductor,
A field effect transistor, wherein the second gate layer is made of a semiconductor having a different work function from the first semiconductor forming the channel forming region. 2. A source region, a drain region, a channel forming region made of a first semiconductor provided in contact with the source region and the drain region, and first and second gate layers provided on the channel forming region. the first gate layer in contact with the channel forming region is made of a second semiconductor having a larger band gap and lower impurity concentration than the first semiconductor; In a field effect transistor made of a material with lower resistance or a semiconductor with a higher impurity concentration than the first semiconductor,
An integrated circuit characterized in that a plurality of field effect transistors in which the second gate layer is made of a semiconductor having a different work function from the first semiconductor constituting the channel forming region are arranged on the same chip.