JPH0263301B2 - - Google Patents

Info

Publication number
JPH0263301B2
JPH0263301B2 JP59195908A JP19590884A JPH0263301B2 JP H0263301 B2 JPH0263301 B2 JP H0263301B2 JP 59195908 A JP59195908 A JP 59195908A JP 19590884 A JP19590884 A JP 19590884A JP H0263301 B2 JPH0263301 B2 JP H0263301B2
Authority
JP
Japan
Prior art keywords
solder
substrate
pads
wettable
melting point
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP59195908A
Other languages
English (en)
Other versions
JPS60119737A (ja
Inventor
Neiru Rakuritsutsu Maaku
Orudonetsu Joze
Josefu Chubiora Piitaa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of JPS60119737A publication Critical patent/JPS60119737A/ja
Publication of JPH0263301B2 publication Critical patent/JPH0263301B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistors
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components
    • H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/093—Connecting or disconnecting other interconnections thereto or therefrom, e.g. connecting bond wires or bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09781—Dummy conductors, i.e. not used for normal transport of current; Dummy electrodes of components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10227—Other objects, e.g. metallic pieces
    • H05K2201/10234—Metallic balls
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/20—Details of printed circuits not provided for in H05K2201/01 - H05K2201/10
    • H05K2201/2036—Permanent spacer or stand-off in a printed circuit or printed circuit assembly
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/04—Soldering or other types of metallurgic bonding
    • H05K2203/0465—Shape of solder, e.g. differing from spherical shape, different shapes due to different solder pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07221—Aligning
    • H10W72/07227—Aligning involving guiding structures, e.g. spacers or supporting members
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07231—Techniques
    • H10W72/07236—Soldering or alloying
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07251—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07251—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting
    • H10W72/07253—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting changes in shapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/221—Structures or relative sizes
    • H10W72/227—Multiple bumps having different sizes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/231—Shapes
    • H10W72/237—Multiple bump connectors having different shapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251—Materials
    • H10W72/252—Materials comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/281—Auxiliary members
    • H10W72/285—Alignment aids, e.g. alignment marks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/29—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/921—Structures or relative sizes of bond pads
    • H10W72/926—Multiple bond pads having different sizes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Wire Bonding (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Description

【発明の詳細な説明】 ［産業上の利用分野］ 本発明は超小型（マイクロミニアチユア）構成
素子を支持板又は基板に半田接続する方法に関す
るものであり、さらに具体的には良好な抵抗対横
方向ストレス比を与えるように縦方向に伸びた接
続体（ジヨイント）を形成するための方法に関す
る。
本発明は基板に対して半導体デバイスをフエイ
スダウン又はフリツプチツプ式にボンデイングす
ることに関係があり、半導体デバイスと支持基板
との間の複数の電気的接続を極めて小さくしかも
密接した半田相互接続よつて行なうことを可能に
する。
［従来技術］ 米国特許第3401126号及び第3429040号は半導体
チツプを支持体にフエイスダウン・ボンデイング
するための「コントロールド・コラプス（つぶ
し）接続」方法を開示している。これらの米国特
許に開示されている事項は半導体チツプの接点領
域及びチツプ支持体の導体上の半田接続可能領域
に金属性半田のパツドを形成することである。チ
ツプ支持体の半田接続可能領域は半田づけ不能の
障壁で囲まれているので、支持体領域及び半導体
デバイス接点領域上の半田が溶融して合体したと
き、表面張力により半導体チツプは支持体の上方
に浮遊する。
集積回路半導体デバイスの技術進歩に伴い個々
の能動素子及び受動素子の寸法が極めて小さくな
り、しかも１つのデバイス中の素子の数が著しく
増加するに至つた。このため、Ｉ／Ｏ端子の数が
増加してデバイスの寸法が著しく大きくなる結果
を生じた。この傾向は今後も続き、端子の密度及
び全体的な数に対して次第に高度の要請が出て来
るであろう。半田接続の利点はＩ／Ｏ端子をデバ
イスの上側表面の実質的に全体に亘つて分散配置
できることである。これは全表面の有効利用を可
能にし、エリア・ボンデイングとして知られてい
る。
集積回路デバイスは半導体デバイスの材料、即
ちシリコンの膨張係数とは異なつた膨張係数を有
する材料で作られた支持基板上に装着されるのが
普通である。使用中にデバイスの構成素子が必然
的に熱を発生し、その熱は半田ボンドを介して移
動するのでデバイス及び支持基板の両方に温度変
動を生じさせる。デバイス及び基板は膨張係数の
相異に起因して、温度変動と共に異なつた量だけ
膨張及び収縮する。これは半田端子にストレスを
生じさせる。動作中に半田ボンドに生じるストレ
スは、(1)温度変動の大きさ、(2)中立点からの距
離、(3)デバイス及び基板の膨張係数の差に正比例
し、半田ボンドの高さ、即ちデバイスと支持基板
との間の間隔に反比例する。事態の厳しさは、実
装密度を一層高めるニーズに順応するため半田端
子の直径が益々小さくなり、全体的な高さも又低
下する事実によつて更に増大する。
今までよりも高密度の端子を有する更に大きい
デバイスを組込む将来の用途に対しても半田端子
の利用を続けるための考えうる解決策として、半
田端子を細長くすればよいことが、米国特許第
3811186号、第3486223号、3921285号及びIBM
TDBの1973年８月号第767頁、1976年９月号第
1178頁、1980年７月号第575頁に開示されている。
高さを同一にした場合、砂時計状（上下間の中間
部がくびれた形状）の半田端子の方が円筒状又は
ビヤ樽状の端子よりもストレス耐力の点で優れて
いることがわかつた。
この現象はIBM Journal of Research and
Development 1969年５月号、Vol.13、No.３、第
261頁に説明されている。
［発明が解決しようとする問題点］ 上述の文献に開示された細長い半田端子を作る
ための方法は実際的でない。即ちそれらに開示さ
れた方法は製造工程を実行する作業者の技巧及び
個人的な能力に存在する点で個人的職人芸を必要
とする。従つて一般的な再現性がなく製造産業上
利用することができなかつた。
［問題点を解決するための手段］ 本発明は集積回路半導体デバイスと支持基板と
の間に背高の細長い半田端子を形成するための新
規な方法を提案する。本発明の方法で形成される
背高の（細長い）半田接続体はデバイス及び基板
の温度変動によつて生じるストレスに耐えること
ができる。
本発明の問題解決手段は、背高の半田端子を形
成するため、(1)半導体デバイスと支持基板との間
に予定の垂直間隔を維持するための手段を配設
し、(2)基板又はデバイス上の各半田ウエツタブ
ル・パツドに対して半田柱体を形成して付着さ
せ、(3)半田ウエツタブル・パツド上に半田マウン
トを有する半導体デバイスを、半田マウントを有
する支持基板上に位置合わせした状態で位置づけ
し、デバイスと基板との間の距離を垂直間隔維持
手段で橋渡しし、予定の間隔を維持した状態に組
合わせた後加熱して半田接続丘及び半田柱体をリ
フロすることにより複数個の砂時計状細長接続体
を形成するステツプを含む。
［実施例］ 第１図のステツプ１はデバイスをボンドできる
代表的な基板１０を示す。セラミツクの基板１０
上には１組の半田ウエツタブル・パツド１２が載
置されている。それらのパツドはピン（図示せ
ず）付のパツドと他の関連デバイスとを相互接続
する内部的に冶金形成されたものでも、上面に冶
金処理で形成されたものでもよい。図を簡潔にす
るため唯一組のパツドだけを図示する。実際は沢
山のデバイスに接続するための多数組のパツドを
持つことができる。冶金形成されたパツドは表面
に置いても、又はもしも望むなら表面及び内部に
置いてもよい。基板１０は一般的な形式の基板を
図示したもので本発明の要部を構成するものでは
ない。一般に基板１０は、それにボンドされるべ
き半導体デバイスを形成するために使用された材
料、即ちシリコンの膨張係数とは異なつた膨張係
数を通常有するセラミツク材料で形成される。
ステツプ２は相対的に高い融点を有する適当な
半田合金で形成された半田柱体１６がボンドされ
た例えばシリコン製の仮基板１４を示す。半田柱
体の代表例は純粋のPb又はPb含有率の極めて高
い半田で形成される。半田柱体１６は融点が327
℃程度の材料にすべきである。各半田柱体１６の
上部表面上に低融点金属の層１８がある。その層
の代表例は400乃至600Åの範囲の厚さと240℃程
度の融点を有する錫である。半田柱体１６は基板
１０上のパツド形状に相当する形状の適当な穴あ
きマスクを仮基板１４上に載置し、その上に半田
合金を適当な所望の深さ、代表的には0.05乃至
0.1mmの深さまで蒸着することによつて形成され
る。低融点の層１８は引続いて柱体１６の上面に
蒸着により付着される。ステツプ３で示すように
柱体１６を有する仮基板１４を反転して、パツド
１２の表面と層１８とが接触するように基板１０
の上面に載置する。そのような組立体を層１８の
融ける温度まで加熱した後冷却して半田柱体１６
をパツド１２と融合させることにより、半田柱体
１６は基板１０へ移される。その後仮基板１４を
除去するとステツプ４で示すような構造体が出来
る。基板１０上にボンドされるべき集積回路半導
体デバイス２０をステツプ５で示す。デバイス２
０は基板１０上の半田パツド１２の形状と合致す
る形状に配列された複数の半田接続丘２２を有す
る。各半田接続丘２２は半田ウエツタブル・パツ
ド構造体２１とその上面に半田リフロされた丘と
より成る。図示の通りデバイス２０の周辺部分は
半田接続丘２２の領域よりも外方へ延びている。
デバイス２０は普通のものであつて、多数の能動
素子及び受動素子を含んでいる。デバイス２０の
周辺部分にはパツド２１と一緒に形成されるのが
普通である半田ウエツタブル・パツド２４が設け
られている。このパツド２４は半導体デバイスと
基板との間の予定の垂直間隔を維持するための手
段の基礎を構成するので、任意の適した個数だけ
設けてよい。一般的にはデバイス構造体当り最少
３パツドが必要であるが、もしも必要ならばそれ
以上設けてもよい。間隔を維持するための手段が
次のステツプ６に示すように組立てられる。パツ
ド２４にかぶさる開口２８を有するマスク２６が
デバイス２０の上面に載置される。半田の薄層３
０が通常の蒸着方法によつてパツド２４の上面に
蒸着される。基板とデバイスの所望間隔に近い直
径を有する金属球３２を開口２８内に入れて、層
３０を融かすように加熱した後冷却して金属球３
２をデバイス２０に接合する。金属球３２は任意
の金属製のものでよいが、銅製でその表面にニツ
ケル被覆した上に金を被覆したものが望ましい。
金属球３２の直径は0.13mm程度が普通である。マ
スク２６を取除いた後に組立体を反転し、ステツ
プ７に示すようにパツド１２上に半田柱体１６を
有する基板１０上の定位置に載置する。図示の通
り金属球３２はデバイスと基板との間に所望の間
隔を維持する台座（スタンド・オフ）となり、デ
バイス上の各Ｉ／Ｏパツドは半田接続丘２２を半
田柱体１６と接触して基板上の対応するパツドと
接続される。次にその組立体を半田柱体１６及び
半田接続丘２２の材料が融ける温度まで加熱する
と、デバイスのパツドと基板のパツドとの間に背
高の細長い砂時計の形の半田接続体３８が形成さ
れる。半田柱体１６及び半田接続丘２２の半田の
総量は、砂時計形の接続体を形成するためパツド
間の間隔を考慮して計算される。
次に第２図は本発明の第２の実施例である第２
のステツプ順序を示す。この実施例の基板１０は
第１の実施例で説明されたような任意の適当な支
持体でよい。基体１０は例えばMLC基板のよう
な非焼結セラミツク基板であつてもよい。開口４
２を有するマスク４０を基板１０の上面に載置
し、台座を形成すべき所望の場所に開口４２を位
置づけする。適当な展剤（ビークル）と混合した
金属粒子、望ましくはモリブデン、タンタル、又
はタングステンのような耐火性材料より成る金属
ペーストを開口４１に詰込んで台座４２，４４を
形成する。詰込み作業に続いてマスク４０を取除
き、組立体を焼結することによりペースト中の展
剤、可塑剤等及び（もしも基板が予め焼結されて
いないならば）グリーン・セラミツク基板１０中
のバインダを追出す。焼結後の台座４２，４４の
高さは基板上に配置されるべきデバイスと基板１
０との間の所望の間隔に相当する。焼結に起因す
る収縮はマスク４０の厚さを増すことにより調節
される。仮基板１４に付着された第２図に示す半
田柱体１６は第１図の実施例で説明したのと同じ
要領で作られる。仮基板１４の半田柱体１６をパ
ツド１２上に載置し、半田柱体１６をパツド１２
に融着するように加熱し、然る後仮基板１４を除
去してステツプ３に示す構造体を残留させる。ス
テツプ４に示すように、半田接続丘２２の設けら
れた半導体デバイスを、その半田接続丘２２と半
田柱体１６が接触するように且つデバイスの周囲
部分が台座４２，４４に接するように、基板上に
載置する。組立体は次に半田素子をリフローする
ため加熱してステツプ５に示すように、半田接続
体３８が引伸ばされて砂時計形の外観を持つ構造
体を形成する。
最初の実施例10において例示した基体へ付着さ
れた球状の台座はもしも望むなら基板１０上に装
着されたパツドへ接着するように変えてもよい。
そればかりか、デバイス又は基板上の何れかの台
座の位置も個々の実施態様に合わせて変更可能で
ある。更に、もしも必要な接続を基板及び半導体
デバイスに作ることが可能ならば、台座それ自身
をＩ／Ｏ端子又は接地端子として利用することが
可能である。
［発明の効果］ 本発明によれば量産方式で製造可能な再現性あ
る背高半田接続体を形成することができ個人的な
技巧依存性から脱脚できる。本発明の方法で形成
される背高半田接続体はデバイス及び基板の温度
変動によつて生じるストレスに耐えることができ
る。
【図面の簡単な説明】
第１図は本発明の第１の実施例における製造過
程を示す図、第２図は本発明の第２の実施例にお
ける製造過程を示す図である。 １０……基板、１２……半田ウエツタブル・パ
ツド、１４……仮基板、１６……半田柱体、１８
……低融点金属層、２０……集積回路半導体デバ
イス、２１……パツド、２２……半田接続丘、２
４……パツド、２６……マスク、２８……開口、
３０……半田薄層、３２……金属球、３８……砂
時計状の半田接続体。

Claims (1)

  1. 【特許請求の範囲】 １ 半導体デバイスの複数個の半田ウエツタブル
    Ｉ／Ｏパツドに設けた半田接続丘を、夫々対応す
    る支持基板の複数個の半田ウエツタブル・パツド
    に電気的に接続するための背高半田接続体を形成
    する方法であつて、 第３の素子である仮基板を用意して、上記支持
    基板の半田ウエツタブル・パツドに対応する上記
    仮基板上の位置に半田柱体を形成し、 上記半田柱体の上部表面上に、それよりも相対
    的に低融点の金属薄層を付着し、 上記半田柱体の上部表面上の低融点の金属薄層
    が、上記支持基板上の半田ウエツタブル・パツド
    と接触するように上記仮基板を上記支持基板上に
    載置し、 上記低融点の金属層が溶融する温度まで過熱
    し、冷却した後、上記仮基板を除去し、 上記半導体デバイスと上記支持基板との間に、
    上記半田柱体の融点では変形しない材料製で、且
    つ上記半田ウエツタブル・パツドの横幅よりも大
    なる高さを有する垂直間隔維持手段を配設し、 上記半田接続丘を有する上記半導体デバイス
    を、上記半田接続丘が上記支持基板のパツドに形
    成された上記半田柱体に整合して接触するように
    且つ上記垂直間隔維持手段が上記半導体デバイス
    と支持基体との間にはさまれるように、上記支持
    基板体上に載置して成る組立体を形成し、 上記垂直間隔維持手段によつて決められる間隔
    を維持した状態で上記組立体を加熱して上記半田
    接続丘及び半田柱体をリフロすることにより複数
    個の砂時計状の背高半田接続体を形成する方法。 ２ 上記半田ウエツタブル・パツドの横幅に対す
    る背高半田接続体の高さの比が１以上であること
    を特徴とする特許請求の範囲第１項記載の背高半
    田接続体を形成する方法。
JP59195908A 1983-11-25 1984-09-20 背高半田接続体を形成する方法 Granted JPS60119737A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US555264 1983-11-25
US06/555,264 US4545610A (en) 1983-11-25 1983-11-25 Method for forming elongated solder connections between a semiconductor device and a supporting substrate

Publications (2)

Publication Number Publication Date
JPS60119737A JPS60119737A (ja) 1985-06-27
JPH0263301B2 true JPH0263301B2 (ja) 1990-12-27

Family

ID=24216611

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59195908A Granted JPS60119737A (ja) 1983-11-25 1984-09-20 背高半田接続体を形成する方法

Country Status (4)

Country Link
US (1) US4545610A (ja)
EP (1) EP0147576B1 (ja)
JP (1) JPS60119737A (ja)
DE (1) DE3478729D1 (ja)

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EP0147576A1 (en) 1985-07-10

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