JPH0273823U - - Google Patents
Info
- Publication number
- JPH0273823U JPH0273823U JP15269288U JP15269288U JPH0273823U JP H0273823 U JPH0273823 U JP H0273823U JP 15269288 U JP15269288 U JP 15269288U JP 15269288 U JP15269288 U JP 15269288U JP H0273823 U JPH0273823 U JP H0273823U
- Authority
- JP
- Japan
- Prior art keywords
- field effect
- effect transistor
- drain electrode
- electrode
- grounded
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005669 field effect Effects 0.000 claims description 13
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims 1
- 238000006243 chemical reaction Methods 0.000 claims 1
- 239000000758 substrate Substances 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Networks Using Active Elements (AREA)
Description
第1図はこの考案の一実施例の構成を示す接続
図、第2図はFETの簡略等価回路図、第3図は
従来のPINダイオードを用いた反射形定位相可
変減衰器の構成を示す接続図、第4図はPINダ
イオードの簡略等価回路である。
図において1は90度位相差ハイブリツト、2
は第1の電界効果トランジスタ、3は第2の電界
効果トランジスタ、4は第1のインダクタ、5は
第2のインダクタ、6はグランド、7は第1の抵
抗、8は第2の抵抗、9は第3の抵抗、10は第
N+1の抵抗、11は第3の電界効果トランジス
タ、12は第4の電界効果トランジスタ、13は
第N+3の電界効果トランジスタ、14はドレイ
ンソース間抵抗、15はドレインソース間容量、
16は第1のPINダイオード、17は第2のP
INダイオード、18は接触抵抗、19は接合抵
抗、20は接合容量である。なお、図中同一符号
は同一または相当部分を示すものとする。
Figure 1 is a connection diagram showing the configuration of an embodiment of this invention, Figure 2 is a simplified equivalent circuit diagram of an FET, and Figure 3 is a configuration of a conventional reflective constant phase variable attenuator using a PIN diode. The connection diagram, FIG. 4, is a simplified equivalent circuit of a PIN diode. In the figure, 1 is a 90 degree phase difference hybrid, 2
is the first field effect transistor, 3 is the second field effect transistor, 4 is the first inductor, 5 is the second inductor, 6 is the ground, 7 is the first resistor, 8 is the second resistor, 9 is the third resistor, 10 is the N+1 resistor, 11 is the third field effect transistor, 12 is the fourth field effect transistor, 13 is the N+3 field effect transistor, 14 is the drain-source resistance, and 15 is the drain Source-to-source capacitance,
16 is the first PIN diode, 17 is the second P
18 is a contact resistance, 19 is a junction resistance, and 20 is a junction capacitance. Note that the same reference numerals in the figures indicate the same or corresponding parts.
Claims (1)
差ハイブリツトの出力2端子の1端子とドレイン
電極が接続されソース電極が接地された第1の電
界効果トランジスタと、上記90度位相差ハイブ
リツトの他の出力端子とドレイン電極が接続され
ソース電極が接地された第2の電界効果トランジ
スタと、上記第1の電界効果トランジスタのドレ
イン電極とソース電極間に接続された第1のイン
ダクタと、上記第2の電界効果トランジスタのド
レイン電極とソース電極間に接続された第2のイ
ンダクタとからなる反射形定位相減衰器と、1端
が上記第1及び第2の電界効果トランジスタのゲ
ート電極に接続された第1の抵抗と、1端がそれ
ぞれソース接地された電界効果トランジスタのド
レイン電極と接続され、他の1端が上記第1及び
第2の電界効果トランジスタのゲート電極に接続
されたN個の抵抗群からなるデイジタルアナログ
変換回路とを、該GaAs基板上に一体形成した
ことを特徴とする定位相デイジタル可変減衰器。 a 90 degree phase difference hybrid, a first field effect transistor whose drain electrode is connected to one of the two output terminals of the 90 degree phase difference hybrid and whose source electrode is grounded, and another output of the 90 degree phase difference hybrid. a second field effect transistor whose terminal and drain electrode are connected and whose source electrode is grounded; a first inductor connected between the drain electrode and the source electrode of the first field effect transistor; and the second field effect transistor. a reflective constant phase attenuator comprising a second inductor connected between the drain electrode and the source electrode of the effect transistor; and a first field effect transistor having one end connected to the gate electrodes of the first and second field effect transistors. from a group of N resistors each having one end connected to the drain electrode of the field effect transistor whose source is grounded and the other end connected to the gate electrode of the first and second field effect transistors. 1. A constant-phase digital variable attenuator, characterized in that a digital-to-analog conversion circuit is integrally formed on the GaAs substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15269288U JPH0273823U (en) | 1988-11-24 | 1988-11-24 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15269288U JPH0273823U (en) | 1988-11-24 | 1988-11-24 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0273823U true JPH0273823U (en) | 1990-06-06 |
Family
ID=31427851
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15269288U Pending JPH0273823U (en) | 1988-11-24 | 1988-11-24 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0273823U (en) |
-
1988
- 1988-11-24 JP JP15269288U patent/JPH0273823U/ja active Pending