JPH027452A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH027452A JPH027452A JP15734088A JP15734088A JPH027452A JP H027452 A JPH027452 A JP H027452A JP 15734088 A JP15734088 A JP 15734088A JP 15734088 A JP15734088 A JP 15734088A JP H027452 A JPH027452 A JP H027452A
- Authority
- JP
- Japan
- Prior art keywords
- film
- silicon oxide
- oxide film
- silicon nitride
- silicon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 14
- 238000000576 coating method Methods 0.000 claims abstract description 8
- 239000011248 coating agent Substances 0.000 claims description 6
- 230000001681 protective effect Effects 0.000 claims description 5
- 239000000758 substrate Substances 0.000 claims description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 18
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 18
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 12
- 229910052782 aluminium Inorganic materials 0.000 abstract description 12
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 9
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 abstract description 9
- 230000000694 effects Effects 0.000 abstract description 4
- 239000011229 interlayer Substances 0.000 abstract description 3
- 238000000034 method Methods 0.000 abstract 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 238000000059 patterning Methods 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a semiconductor device.
従来の半導体装置の半導体チップ保護膜の構造を図面を
参照して説明する。The structure of a conventional semiconductor chip protective film of a semiconductor device will be explained with reference to the drawings.
第２図は従来の半導体チップの一例の断面図である。FIG. 2 is a cross-sectional view of an example of a conventional semiconductor chip.
シリコン基板の上にシリコン酸化膜２を設け、第１アル
ミニウム配線３を形成する。全面にシリコン酸化膜４を
被覆し、アルミニウム配線３の上のシリコン酸化膜４を
開口し、層間接続用のスルーホール５を設け、第２アル
ミニウム配線６を形成する。この上にシリコン酸化膜７
、シリコン窒化膜８を順次堆積する。A silicon oxide film 2 is provided on a silicon substrate, and a first aluminum wiring 3 is formed. The entire surface is covered with a silicon oxide film 4, the silicon oxide film 4 above the aluminum wiring 3 is opened, a through hole 5 for interlayer connection is provided, and a second aluminum wiring 6 is formed. On top of this is a silicon oxide film 7.
, a silicon nitride film 8 is sequentially deposited.
上述した従来の半導体装置は、スルーホール５において
、シリコン窒化膜７のカバレッジが悪化し、膜厚が薄く
なって、この半導体チップをモールドパッケージに組ん
だ時、耐湿性が劣化するという欠点があった。The conventional semiconductor device described above has the disadvantage that the coverage of the silicon nitride film 7 deteriorates in the through hole 5, the film thickness becomes thinner, and the moisture resistance deteriorates when this semiconductor chip is assembled into a mold package. Ta.
本発明は、半導体基板上に形成された多層配線と、該多
層配線を保護する保護膜とが形成されている半導体装置
において、前記保護膜が第１絶縁膜と、該第１絶縁膜の
凹部にのみ選択的に残存せしめな塗布膜と、前記第１絶
縁膜上に形成された耐湿性の第２絶縁膜とから成るもの
である。The present invention provides a semiconductor device including a multilayer wiring formed on a semiconductor substrate and a protective film that protects the multilayer wiring, in which the protective film has a first insulating film and a recessed part of the first insulating film. The second insulating film is composed of a coating film that is selectively left only on the first insulating film, and a moisture-resistant second insulating film formed on the first insulating film.
次に、本発明の実施例について図面を参照して説明する
。Next, embodiments of the present invention will be described with reference to the drawings.
第１図は本発明の一実施例の断面図である。FIG. 1 is a sectional view of an embodiment of the present invention.
シリコン基板１上に膜厚１．０μｍのシリコン酸化膜２
を形成する。次に、膜厚０．６μｍ程度のアルミニウム
を被着し、パターニングして第１アルミニウム配線３を
形成する。その上に膜厚０．８μｍ程度のシリコン酸化
膜４を形成し、層間接続用のスルーホール５を形成する
。次に、膜厚１．０μｍ程度のアルミニウムを被着し、
パターニングして第２アルミニウム配線６を形成する。Silicon oxide film 2 with a film thickness of 1.0 μm on a silicon substrate 1
form. Next, aluminum with a thickness of about 0.6 μm is deposited and patterned to form the first aluminum wiring 3. A silicon oxide film 4 having a thickness of about 0.8 μm is formed thereon, and through holes 5 for interlayer connections are formed. Next, aluminum with a film thickness of about 1.0 μm is deposited,
A second aluminum wiring 6 is formed by patterning.
次に、膜厚０．５μｍ程度のシリコン酸化膜７を形成す
る。そして、塗布膜９を塗布法で形成し、異方性エッチ
バックをする事によりシリコン酸化膜７の凹部にのみ塗
布膜９を残存せしめる。Next, a silicon oxide film 7 having a thickness of about 0.5 μm is formed. Then, the coating film 9 is formed by a coating method and anisotropically etched back so that the coating film 9 remains only in the recessed portions of the silicon oxide film 7.
最後に、膜厚０．５μｍ程度のシリコン窒化膜８を形成
する。Finally, a silicon nitride film 8 having a thickness of about 0.5 μm is formed.
上記実施例においては第１絶縁膜としてシリコン酸化膜
を用いたが、シリコン酸化膜の代りに、シリコン窒化膜
を用いることができ、より一層耐湿性効果を高めること
ができる。In the above embodiment, a silicon oxide film was used as the first insulating film, but a silicon nitride film can be used instead of the silicon oxide film, and the moisture resistance effect can be further enhanced.
以上説明したように、本発明は、シリコン酸化膜の凹部
に塗布膜を選択的に残存せしめ、その上にシリコン窒化
膜を形成するので、その膜厚は、均一となり、半導体チ
ップをモールドパッケージに組んだ時にも耐湿性を確保
できる効果がある。As explained above, in the present invention, a coating film is selectively left in the recesses of a silicon oxide film, and a silicon nitride film is formed thereon, so that the film thickness is uniform and the semiconductor chip is molded into a package. It has the effect of ensuring moisture resistance even when assembled.
第１図は本発明の一実施例の断面図、第２図は従来の半
導体チップの一例の断面図である。
１・・・シリコン基板、２，４．７・・・シリコン酸化
膜、３・・・第１アルミニウム配線、５・・・スルーホ
ール、６・・・第２アルミニウム配線、８・・・シリコ
ン窒化膜、９・・・塗布膜。FIG. 1 is a sectional view of an embodiment of the present invention, and FIG. 2 is a sectional view of an example of a conventional semiconductor chip. DESCRIPTION OF SYMBOLS 1... Silicon substrate, 2,4.7... Silicon oxide film, 3... First aluminum wiring, 5... Through hole, 6... Second aluminum wiring, 8... Silicon nitride Film, 9... Coating film.
Claims (1)
護する保護膜とが形成されている半導体装置において、
前記保護膜が第１絶縁膜と、該第１絶縁膜の凹部にのみ
選択的に残存せしめた塗布膜と、前記第１絶縁膜上に形
成された耐湿性の第２絶縁膜とから成ることを特徴とす
る半導体装置。In a semiconductor device in which a multilayer wiring formed on a semiconductor substrate and a protective film that protects the multilayer wiring are formed,
The protective film comprises a first insulating film, a coating film selectively left only in the recessed portions of the first insulating film, and a moisture-resistant second insulating film formed on the first insulating film. A semiconductor device characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15734088A JPH027452A (en) | 1988-06-24 | 1988-06-24 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15734088A JPH027452A (en) | 1988-06-24 | 1988-06-24 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH027452A true JPH027452A (en) | 1990-01-11 |
Family
ID=15647550
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15734088A Pending JPH027452A (en) | 1988-06-24 | 1988-06-24 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH027452A (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62150852A (en) * | 1985-12-25 | 1987-07-04 | Oki Electric Ind Co Ltd | Manufacture of semiconductor element |
-
1988
- 1988-06-24 JP JP15734088A patent/JPH027452A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62150852A (en) * | 1985-12-25 | 1987-07-04 | Oki Electric Ind Co Ltd | Manufacture of semiconductor element |
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