JPH0284440U - - Google Patents

Description

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the circuit of the present invention;
2 and 3 are circuit diagrams for explaining the operation of the circuit of the present invention, and FIGS. 4 to 6 are waveform diagrams for explaining the present invention. 1, 2... operational amplifier, 3... inverter, 4
... Phase comparator, 5 ... Pulse width/voltage conversion circuit, 6 ... Envelope detection circuit, 7 ... Integral synthesis circuit,
8... Voltage controlled oscillator, 9... Phase comparator, 12
...Correction error detection circuit, R1 to R16...Resistance,
C1 to C7...Capacitor, C8...Varicap, L1...Coil, Q1, Q2...Transistor, Q3, Q4...FET.

Claims (1)

[Claims for Utility Model Registration] A clock forming circuit for forming, from a digital data signal, a forming clock signal corresponding to a data clock that controls the inversion timing of the digital data signal; a phase difference information output means for comparing the phases and outputting a phase difference information signal whose level changes according to the phase difference; and a level increasing in accordance with the phase difference information signal;
and a first envelope signal whose level decreases according to a predetermined decreasing characteristic when the level of the phase difference information signal rapidly decreases; an envelope signal output means for outputting a second envelope signal whose level increases with a predetermined increase characteristic when the level increases rapidly; addition information and addition integral information of the first and second envelope signals; A clock forming circuit comprising: corrected error detecting means for outputting a corrected error information signal containing the corrected error information signal; and forming clock signal output means for outputting the forming clock signal whose frequency is controlled based on the corrected error information signal. .