JPH0284804A - Gain control circuit - Google Patents

Gain control circuit

Info

Publication number
JPH0284804A
JPH0284804A JP23700788A JP23700788A JPH0284804A JP H0284804 A JPH0284804 A JP H0284804A JP 23700788 A JP23700788 A JP 23700788A JP 23700788 A JP23700788 A JP 23700788A JP H0284804 A JPH0284804 A JP H0284804A
Authority
JP
Japan
Prior art keywords
current source
gain control
control circuit
collector
transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP23700788A
Other languages
Japanese (ja)
Inventor
Tadaaki Yamada
匡章 山田
Isao Nakayama
勲 中山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP23700788A priority Critical patent/JPH0284804A/en
Publication of JPH0284804A publication Critical patent/JPH0284804A/en
Pending legal-status Critical Current

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  • Control Of Amplification And Gain Control (AREA)

Abstract

PURPOSE:To facilitate direct connection to the next stage keeping an output DC level constant by providing a circuit which inputs a difference between a reference current to a variable gain control circuit. CONSTITUTION:An input signal is supplied to the base of the first transistor TR Q1 of a differential amplifier in a gain control circuit, and a first variable current source IA is connected to the emitter of the TR Q1 connected to a second TR Q2, and a load resistor R1 is connected to the collector of the TR Q1. Also, the collector of a third TR Q4 is connected to that of the TR Q1, and a current mirror is comprised of the TR Q4 and a fourth TR Q5, and a second variable current source IB is provided at the base and collector of the TR Q4. When the gain of the amplifier of operating format is varied by varying the current source IA of the gain control circuit, the output DC level can be kept constant by the TRs Q4 and Q5 and the second current source IB. Then, a discharge circuit which supplies the difference between the reference current generated by varying the current source IA can be formed.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は可変利得制御回路に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a variable gain control circuit.

〔従来の技術〕[Conventional technology]

第3図は従来の可変利得増幅回路の一例の回路図である
入力信号はトランジスタQ・10ベースに入力され、こ
のQlとQ、及び可変電流源IA>負荷抵抗R8により
可変利得増幅回路を構成しており、可変電流源工えの電
流値を変化させる事により、この増幅器の利得を可変さ
せる。その利得を算出すると電流源工、の電流値を工え
とすると、と表わされる。
Figure 3 is a circuit diagram of an example of a conventional variable gain amplifier circuit.The input signal is input to the base of transistor Q10, and a variable gain amplifier circuit is constructed by Ql and Q, and variable current source IA>load resistor R8. The gain of this amplifier is varied by changing the current value of the variable current source. Calculating the gain is expressed as, if the current value of the current source is the current value.

この式より、工、の値を可変させる事により利得が可変
する。
From this equation, the gain can be varied by varying the value of .

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来の可変利得増幅回路は利得を可変させる事
により、出力DCレベルが変動し、次段に直結する事が
容易でないという欠点がある。
The above-mentioned conventional variable gain amplifier circuit has the disadvantage that by varying the gain, the output DC level fluctuates, and it is not easy to connect it directly to the next stage.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の可変利得増幅回路は、入力信号がベースに供給
される第1のトランジスタと該第10トランジスタと差
動増幅器を構成する第2トランジスタと該第1,2のエ
ミッタに接続される第1の電流源と該第1のトランジス
タのコレクタに接続される第1の負荷抵抗と該第1のト
ランジスタのコレクタにコレクタが接続されている第3
のトランジスタと該第3のトランジスタとカレントミラ
ーな構成する第4のトランジスタと該第4のトランジス
タのベース・コレクタに接続される第2の電流源を備え
、該第1の電流源を可変し、該第1及び第2のトランジ
スタからなる差動増幅器の利得を可変させるに際し、該
第3及び4のトランジスタ並びに該第2の電流源により
出力DCレベルを一定に保つ回路を有する。
The variable gain amplifier circuit of the present invention includes a first transistor to which an input signal is supplied to the base, a second transistor forming a differential amplifier with the tenth transistor, and a first transistor connected to the first and second emitters. a current source, a first load resistor connected to the collector of the first transistor, and a third resistor, the collector of which is connected to the collector of the first transistor.
a fourth transistor configured as a current mirror with the third transistor; and a second current source connected to the base and collector of the fourth transistor, the first current source being variable; A circuit is provided for keeping the output DC level constant using the third and fourth transistors and the second current source when varying the gain of the differential amplifier made up of the first and second transistors.

このように、可変電流源工、を可変させる事により生ず
る基準電流の差分を供給するはき出し回路を有する事に
よって、出力DCレベルを一定に保つことができる。
In this way, the output DC level can be kept constant by providing the output circuit that supplies the difference in the reference current generated by varying the variable current source.

〔実施例〕〔Example〕

次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第1図は本発明の原理回路図である。すなわち、第3図
の従来例に対し、トランジスタQ、、Q、。
FIG. 1 is a circuit diagram of the principle of the present invention. That is, in contrast to the conventional example shown in FIG. 3, transistors Q, ,Q,.

抵抗R4,R5によるカレントミラー回路とい利得制御
信号に応じた電流源I3とが設けられている。すなわち
ベースに信号が入力される差動増幅回路(Ql、QI 
R1)とこの差動増幅回路の利得を可変させる可変電流
源(IA)及び出力DCレベルを一定に保たせる為のは
き出し回路を(IB。
A current mirror circuit including resistors R4 and R5 and a current source I3 corresponding to a gain control signal are provided. In other words, a differential amplifier circuit (Ql, QI
R1), a variable current source (IA) that changes the gain of this differential amplifier circuit, and an output circuit (IB) that keeps the output DC level constant.

Q4. Ql、 R4,R8)有する。Q4. Ql, R4, R8).

第2図は具体的な一実施例である。トランジスタQl、
Q6はそれぞれ電流源を構成している。
FIG. 2 shows a specific example. transistor Ql,
Q6 each constitutes a current source.

今、Q、のベース電位をVAとすると% Qsのコレク
タ電流は、 利得は ここで 工。
Now, if the base potential of Q is VA, then the collector current of Qs is %.The gain is calculated here.

L= ・・・・・・(3) (1)、 (2)、 (3)式より 次に本回路において出力DC電圧を求めると、Vo=V
cc−Rt ・I y        ・・”(1)こ
こで工、は次式で表わされる。(1,≧工。の場合) I?=II  L=L−Ii=L−Is+I。  ・・
・・・・(2)又、R2= 2 Rsと設定する為 A I s ”     = I +          
・・・・・・(3)(3)式と(2)式より L=I。            ・・・・・・(4)
よってR3には常に工。が流れる為出力DC電圧v0は
一定に保たれる。
L= ・・・・・・(3) Next, calculate the output DC voltage in this circuit from equations (1), (2), and (3). Vo=V
cc-Rt ・I y ..." (1) Here, the work is expressed by the following formula. (In the case of 1, ≧ work.) I?=II L=L-Ii=L-Is+I.
...(2) Also, to set R2 = 2 Rs, A I s ” = I +
...(3) From equations (3) and (2), L=I.・・・・・・(4)
Therefore, R3 is always machined. flows, so the output DC voltage v0 is kept constant.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、基準電流工。との差分を
流し込む回路を有する事により、出力DCレベルを一定
に保つことができ、次段と容易に直結できる効果がある
As explained above, the present invention is a standard electrician. By having a circuit that inputs the difference between the two, the output DC level can be kept constant, and there is an effect that it can be easily directly connected to the next stage.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の原理回路図、第2図は具体的な一実施
例の回路図、第3図は従来例の回路図である。 a・・・・・・入力端子、b・・・・・・出力端子、C
・・・・・・電源端子、d・・・・・・接地端子、Q1
〜Q6・・・・・・トランジスタ% R+〜R6・・・
・・・抵抗、■・・・・・・ボリュウム、■。・・・・
・・定電流源、工え・工、・・・・・・可変電流源、V
A・・・・・・Q、及びQ6のベース電位、■。・・・
・・・出力DC電位。 代理人 弁理士  内 原   晋
FIG. 1 is a circuit diagram of the principle of the present invention, FIG. 2 is a circuit diagram of a specific embodiment, and FIG. 3 is a circuit diagram of a conventional example. a...Input terminal, b...Output terminal, C
...Power terminal, d...Ground terminal, Q1
~Q6...Transistor% R+~R6...
...Resistance, ■...Volume, ■.・・・・・・
・・Constant current source, work・・・・・variable current source, V
A...Base potential of Q and Q6, ■. ...
...Output DC potential. Agent Patent Attorney Susumu Uchihara

Claims (1)

【特許請求の範囲】[Claims] 差動型式に接続されベース間に入力信号が供給される第
1および第2のトランジスタと、これら第1および第2
のトランジスタのエミッタ結合点に接続され利得制御信
号に応じた電流を発生する第1の電流源と、前記利得制
御信号に応じた電流を発生する第2の電流源と、前記第
2の電流源に入力端が接続され前記第1のトランジスタ
のコレクタに出力端が接続されたカレントミラー回路と
を備え、出力の直流レベルを一定に保つ事を特徴とする
利得制御回路。
first and second transistors connected in a differential manner and having an input signal supplied between their bases;
a first current source that is connected to the emitter coupling point of the transistor and generates a current according to the gain control signal; a second current source that generates a current according to the gain control signal; and the second current source. A gain control circuit comprising: a current mirror circuit having an input end connected to the collector of the first transistor and an output end connected to the collector of the first transistor, the gain control circuit maintaining a constant output DC level.
JP23700788A 1988-09-20 1988-09-20 Gain control circuit Pending JPH0284804A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23700788A JPH0284804A (en) 1988-09-20 1988-09-20 Gain control circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23700788A JPH0284804A (en) 1988-09-20 1988-09-20 Gain control circuit

Publications (1)

Publication Number Publication Date
JPH0284804A true JPH0284804A (en) 1990-03-26

Family

ID=17009004

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23700788A Pending JPH0284804A (en) 1988-09-20 1988-09-20 Gain control circuit

Country Status (1)

Country Link
JP (1) JPH0284804A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100801563B1 (en) * 2006-12-04 2008-02-11 한국전자통신연구원 Variable gain amplifier

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6148208A (en) * 1984-08-13 1986-03-08 Rohm Co Ltd Automatic gain control circuit
JPH0265513A (en) * 1988-08-31 1990-03-06 Nec Home Electron Ltd Variable resistor circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6148208A (en) * 1984-08-13 1986-03-08 Rohm Co Ltd Automatic gain control circuit
JPH0265513A (en) * 1988-08-31 1990-03-06 Nec Home Electron Ltd Variable resistor circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100801563B1 (en) * 2006-12-04 2008-02-11 한국전자통신연구원 Variable gain amplifier

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