JPH0355908A - Gain control amplifier circuit - Google Patents

Gain control amplifier circuit

Info

Publication number
JPH0355908A
JPH0355908A JP19175589A JP19175589A JPH0355908A JP H0355908 A JPH0355908 A JP H0355908A JP 19175589 A JP19175589 A JP 19175589A JP 19175589 A JP19175589 A JP 19175589A JP H0355908 A JPH0355908 A JP H0355908A
Authority
JP
Japan
Prior art keywords
current
collector
gain control
transistor
trs
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP19175589A
Other languages
Japanese (ja)
Other versions
JP3049712B2 (en
Inventor
Nobutaka Amano
信孝 天野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP1191755A priority Critical patent/JP3049712B2/en
Publication of JPH0355908A publication Critical patent/JPH0355908A/en
Application granted granted Critical
Publication of JP3049712B2 publication Critical patent/JP3049712B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Control Of Amplification And Gain Control (AREA)

Abstract

PURPOSE:To obtain a sufficiently large output amplitude even when power voltage is low by varying the current flowing to a load in response to the gain and decreasing a voltage drop caused in a load even when the gain is increased. CONSTITUTION:Bases of transistors(TRs) Q10, Q11 being components of a differential circuit connect to bases of TRs Q3, Q4 to detect the ratio of collector currents IC3, IC4 of the TRs Q3, Q4. The collector current of the TR Q10 results in a current (i) flowing to the collector of the Tr Q4 through TRs Q8, Q9 forming a current mirror circuit to decrease the voltage drop of a resistor R3. When currents I1, I4 of constant current sources 2, 5 are set to proper values by taking a power voltage and output amplitude into account, the output amplitude is increased.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は利得制御増幅回路に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a gain control amplifier circuit.

〔従来の技術〕[Conventional technology]

従来、この種の増幅回路としては第2図に示す回路が知
られている。第2図の動作を説明すると、トランジスタ
Ql,Q2で構成される差動回路の出力電流工。2が負
荷抵抗R,に流れる量をトランジスタQl,Q4の差動
回路で制御して入力端子1からみた出力端子6の利得を
変化させている。利得の制御は電源10.11の電圧差
を抵抗Rs,R.で電流に変換し、その電流をダイオー
ドDl,D2で電圧に変換して差動回路を構或するトラ
ンジスタQs,Qtのベースに供給することで、電源1
1の変化を利得の変化にしている。
Conventionally, a circuit shown in FIG. 2 has been known as this type of amplifier circuit. To explain the operation of FIG. 2, it is the output current of a differential circuit composed of transistors Ql and Q2. The gain of the output terminal 6 as seen from the input terminal 1 is changed by controlling the amount of 2 flowing through the load resistor R by a differential circuit of transistors Ql and Q4. To control the gain, the voltage difference between the power supplies 10 and 11 is controlled by resistors Rs and R. The power source 1
A change of 1 is treated as a change in gain.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来の利得制御増幅回路では,利得を上げると
負荷抵抗R,に流れる電流Ic4が多くなるため、R,
の電圧降下が大きくなり、出力信号の動作電位が下がる
ため、電源電圧が低いとトランジスタQ4のコレクター
エミッタ間電圧■。.が確保できなくなり、出力信号が
負方向に振れなくなるという欠点がある。
In the conventional gain control amplifier circuit described above, when the gain is increased, the current Ic4 flowing through the load resistor R, increases;
As the voltage drop increases and the operating potential of the output signal decreases, when the power supply voltage is low, the collector-emitter voltage of transistor Q4 increases. .. This has the disadvantage that the output signal cannot swing in the negative direction.

本発明の目的は、電源電圧が低い場合に利得をあげても
出力振幅が大きくとれることが可能な利得制御増幅回路
を提供することにある。
SUMMARY OF THE INVENTION An object of the present invention is to provide a gain control amplifier circuit that can provide a large output amplitude even when the gain is increased when the power supply voltage is low.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の利得制御増幅回路は、差動形式に接続された第
1及び第2のトランジスタと、これら第1及び第2のト
ランジスタのエミッタ結合点に入力信号電流を供給する
手段と、前記第1のトランジスタのコレクタから出力信
号を得るための負荷と、前記第1及び第2のトランジス
タのベース間に利得制御電圧を供給する手段と、前記利
得制御電圧を受け前記利得制御電圧に応じた前記第1の
トランジスタ内のコレクタ電流の変化と同相の変化を呈
する電流を発生する手段と、この手段からの電流を入力
端に受け前記第1のトランジスタのコレクタに出力端が
接続された電流ミラー回路とを有することを特徴とする
。
The gain control amplifier circuit of the present invention includes first and second transistors connected in a differential manner, means for supplying an input signal current to the emitter junction of the first and second transistors, and the first transistor. a load for obtaining an output signal from the collector of the transistor; means for supplying a gain control voltage between the bases of the first and second transistors; means for generating a current exhibiting a change in phase with a change in collector current in the first transistor; and a current mirror circuit having an input terminal receiving the current from the means and having an output terminal connected to the collector of the first transistor. It is characterized by having the following.

〔実施例〕 次に、本発明について図面を参照して説明する。〔Example〕 Next, the present invention will be explained with reference to the drawings.

第1図は本発明の一実施例を説明するための回路図であ
り、第2図で説明した従来例にトランジスタQs,Qs
からなるカレントミラー回路,トランジスタQ,。,Q
11からなる差動回路及び定電流幅5を追加したもので
ある。
FIG. 1 is a circuit diagram for explaining one embodiment of the present invention, and the conventional example explained in FIG.
A current mirror circuit consisting of a transistor Q. ,Q
11 and a constant current width 5 are added.

追加回路の動作としては、トランジスタQ1。,Qll
で構成される差動回路のベースをトランジスタQi,Q
4のベースに接続することでトランジスタQ3,Q4の
コレクタ電流工。3y I。4の比を検出し、トランジ
スタQ1。のコレクタ電流をカレントミラー回路を構或
するQ a , Q sによりトランジスタQ4のコレ
クタに電流iを流し込むことにより、R,の電圧降下を
減少させている。ここで定電流源2と5の電流値II,
I4を電源電圧、出力振幅を考慮した適正な値に設定す
れば、出力振幅を大きくとることができる. 〔発明の効果〕 以上説明したように本発明は、利得に応じて負荷に流れ
る電流を変化させ利得を大きくした場合でも負荷により
生じる電圧降下を減少することができるため、電源電圧
が低い時でも、充分大きい出力振幅を得ることが可能と
なる。
As for the operation of the additional circuit, the transistor Q1. ,Qll
The base of the differential circuit composed of
By connecting to the base of 4, the collector current of transistors Q3 and Q4 is connected. 3y I. Detecting the ratio of 4, transistor Q1. By flowing current i into the collector of transistor Q4 through Q a and Q s forming a current mirror circuit, the voltage drop across R is reduced. Here, the current values II of constant current sources 2 and 5,
If I4 is set to an appropriate value that takes into account the power supply voltage and output amplitude, the output amplitude can be increased. [Effects of the Invention] As explained above, the present invention can reduce the voltage drop caused by the load even when the gain is increased by changing the current flowing through the load according to the gain, so even when the power supply voltage is low. , it becomes possible to obtain a sufficiently large output amplitude.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例を説明するための回路図、第
2図は従来の利得制御増幅回路を説明するための回路図
である。 1・・・・・・入力端子、2〜5・・・・・・定電流源
、6・・・・・・出力端子、7・・・・・・高位側電源
端子、8・・・・・・定位側電源端子、Q1〜Ql1・
・・・・・トランジスタ、Rl〜R6・・・・・・抵抗
。
FIG. 1 is a circuit diagram for explaining an embodiment of the present invention, and FIG. 2 is a circuit diagram for explaining a conventional gain control amplifier circuit. 1...Input terminal, 2-5...Constant current source, 6...Output terminal, 7...High-level power supply terminal, 8...・Localization side power supply terminal, Q1~Ql1・
...Transistor, Rl to R6...Resistance.

Claims (1)

【特許請求の範囲】[Claims]  差動型式に接続された第1及び第2のトランジスタと
、これら第1及び第2のトランジスタのエミッタ結合点
に入力信号電流を供給する手段と、前記第1のトランジ
スタのコレクタから出力信号を得るための負荷と、前記
第1及び第2のトランジスタのベース間に利得制御電圧
を供給する手段と、前記利得制御電圧を受け前記利得制
御電圧に応じた前記第1のトランジスタ内のコレクタ電
流の変化と同相の変化を呈する電流を発生する手段と、
この手段からの電流を入力端に受け前記第1のトランジ
スタのコレクタに出力端が接続された電流ミラー回路と
を有することを特徴とする利得制御増幅回路。
first and second transistors connected in a differential manner, means for supplying an input signal current to the emitter junction of the first and second transistors, and obtaining an output signal from the collector of the first transistor; means for supplying a gain control voltage between the bases of the first and second transistors; and receiving the gain control voltage and varying a collector current in the first transistor in response to the gain control voltage. means for generating a current exhibiting a change in phase with
A gain control amplifier circuit comprising: a current mirror circuit whose input terminal receives the current from the means and whose output terminal is connected to the collector of the first transistor.
JP1191755A 1989-07-24 1989-07-24 Gain control amplifier circuit Expired - Lifetime JP3049712B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1191755A JP3049712B2 (en) 1989-07-24 1989-07-24 Gain control amplifier circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1191755A JP3049712B2 (en) 1989-07-24 1989-07-24 Gain control amplifier circuit

Publications (2)

Publication Number Publication Date
JPH0355908A true JPH0355908A (en) 1991-03-11
JP3049712B2 JP3049712B2 (en) 2000-06-05

Family

ID=16279967

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1191755A Expired - Lifetime JP3049712B2 (en) 1989-07-24 1989-07-24 Gain control amplifier circuit

Country Status (1)

Country Link
JP (1) JP3049712B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0437209A (en) * 1990-05-31 1992-02-07 Nec Home Electron Ltd Gain control driving circuit
US8230173B2 (en) 2008-03-14 2012-07-24 Fujitsu Semiconductor Limited Cache memory system, data processing apparatus, and storage apparatus

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0437209A (en) * 1990-05-31 1992-02-07 Nec Home Electron Ltd Gain control driving circuit
US8230173B2 (en) 2008-03-14 2012-07-24 Fujitsu Semiconductor Limited Cache memory system, data processing apparatus, and storage apparatus

Also Published As

Publication number Publication date
JP3049712B2 (en) 2000-06-05

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