JPH029443U - - Google Patents

Info

Publication number
JPH029443U
JPH029443U JP1988087701U JP8770188U JPH029443U JP H029443 U JPH029443 U JP H029443U JP 1988087701 U JP1988087701 U JP 1988087701U JP 8770188 U JP8770188 U JP 8770188U JP H029443 U JPH029443 U JP H029443U
Authority
JP
Japan
Prior art keywords
chip
heat dissipation
insertion hole
conductive material
attached
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1988087701U
Other languages
English (en)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1988087701U priority Critical patent/JPH029443U/ja
Publication of JPH029443U publication Critical patent/JPH029443U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Description

【図面の簡単な説明】
第1図は本考案に係るICチツプ放熱構造の実
施例を示す断面図、第2図は第1図の中央縦断面
図である。 1……ICチツプ、2……回路基板、10……
挿通孔、12……伝導材、13……放熱フイン。

Claims (1)

    【実用新案登録請求の範囲】
  1. ICチツプが取付けられる回路基板に挿通孔を
    穿孔し、この挿通孔に熱伝導性の良好な材質で形
    成された伝導材を挿通して、伝導材の一端をIC
    チツプに当接すると共に他端に放熱フインを取付
    けてなるICチツプ放熱構造。
JP1988087701U 1988-06-30 1988-06-30 Pending JPH029443U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1988087701U JPH029443U (ja) 1988-06-30 1988-06-30

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1988087701U JPH029443U (ja) 1988-06-30 1988-06-30

Publications (1)

Publication Number Publication Date
JPH029443U true JPH029443U (ja) 1990-01-22

Family

ID=31312302

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1988087701U Pending JPH029443U (ja) 1988-06-30 1988-06-30

Country Status (1)

Country Link
JP (1) JPH029443U (ja)

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