JPH03142876A - Read only memory device and manufacture thereof - Google Patents

Abstract

PURPOSE:To obtain a highly integrated read only memory by forming a plurality of electrode layers which are extending in the approximately vertical direction on a thin insulating film between thick insulating films, selectively introducing impurities on the surface of a semiconductor substrate at the lower part, and forming a program. CONSTITUTION:A plurality of first polysilicon layers 103 which are the first electrode layers in parallel strip patterns are formed in the X direction which is orthogonally intersected with a thick oxide film 102. Second polysilicon layers 104 which are the second electrode layers are formed. The first polysilicon layers 103 are formed in the parallel strip pattern, and an interval l1 is provided between the neighboring patterns. A part of the edge part of the second polysilicon layer 104 in the Y direction is overlapped on the edge part of the first polysilicon layer 103 at the same plane. Therefore, memory transistors are formed in parallel without the interval in the Y direction. An approximately square pattern 105 is the window part of a mask for a program formed by ion implantation in the lower part of the first polysilicon layer 103.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a read only memory device 777 that stores data in each transistor of a memory cell array and reads and uses the data.
y) and its manufacturing method, and particularly relates to a read-only memory device having a NOR type cell and its manufacturing method.

[Summary of the invention]

The present invention provides a read-only memory device having a NOR type cell and a method for manufacturing the same, in which a plurality of thick kjA edge films are formed on a semiconductor substrate in parallel with a band-like pattern, and a layer opposite to the semiconductor substrate is formed at the bottom of a plurality of thick kjA edge films. While forming a ghost-shaped impurity region, a plurality of electrode layers extending in a direction substantially perpendicular to the pattern are formed on a thin insulating film between the thick insulating films, and a semiconductor substrate below the electrode layers is formed. A highly integrated read-only memory device is obtained by selectively introducing impurities into the surface of the device for programming.

[Conventional technology]

With the spread of office automation equipment, computers, etc., read-only memory devices that store large amounts of data and read and use them when necessary are required to have larger capacities.

By the way, as an example of a conventional highly integrated read-only memory device, there is a NAND with a so-called multi-gate structure.
Type cell read-only memory devices are known (eg, Monthly Se+wiconductor N).

rld 1987 IO issue, pages 33-38, "8M and 16M mask ROM using shallow trenches"), this NAND type cell has two polysilicon layers as gate electrodes, and the second layer Such a NAND cell, in which the channel region under the polysilicon layer is a trench, has a memory cell structure in which 8 to 16 transistors are arranged in series.

[What the invention tries to solve! i! [Problem] By the way, in the above-mentioned NAND cell, if the degree of integration is to be further increased, it is necessary to increase the number of transistors connected in series.

However, when the number of transistors connected in series increases, the driving ability of the memory cell decreases in inverse proportion to the number of transistors.

On the other hand, a NOR type cell in which transistors are connected in parallel does not suffer from the problem of a decrease in the driving ability of a memory cell, but it is difficult to achieve a high degree of integration equivalent to that of the NAND type cell.

Therefore, the present invention is based on the above-mentioned technical! In view of the problem, it is an object of the present invention to provide a read-only memory device that is highly integrated and has a high memory cell driving ability, and a method for manufacturing the same.

[Means to solve the problem]

In order to achieve the above object, the read-only memory device of the present invention includes a plurality of thick first films formed in a strip pattern parallel to each other on the surface of a first conductivity type semiconductor substrate.
The insulating film and their first absolute aI! ! is formed on the surface of the semiconductor substrate between the second conductivity type impurity $5 region formed in the semiconductor substrate below and the first insulating film, and is thinner than the first insulating film. the second insulating film and the second insulating film; It has an electrode layer formed on the film in a plurality of strip-shaped patterns extending in a direction substantially perpendicular to the pattern of the first insulating film and parallel to each other. The electrode layer is
It may be a single layer, two layers or more.

In the case of two layers, the pattern of the second electrode layer of the upper layer may be formed between the band-shaped patterns of the first electrode layer of the lower layer; In the read-only memory device of the present invention, the surface of the semiconductor substrate in the region of the electrode layer may be cut deeper than the surface of the semiconductor substrate in the first electrode layer. Impurities are selectively introduced into the wafer, and programming is performed by introducing the impurities. The impurity introduced is, for example, an impurity of the same first conductivity type as the substrate.

Next, a method for manufacturing such a read-only memory device includes a step of forming an oxidation-resistant film having a strip pattern parallel to each other on the surface of a first conductivity type semiconductor substrate, and a step of forming an oxidation-resistant film in a manner consistent with the oxidation-resistant film. a step of introducing impurities of a second conductivity type into the surface of the semiconductor substrate; a step of oxidizing the surface of the semiconductor substrate using the oxidation-resistant film as a mask to form a thick first oxide film; a step of removing an oxidation-resistant film from above the semiconductor substrate; a step of forming a second oxide film thinner than the first oxide film in a region other than the first oxide film of the semiconductor substrate; forming on the second oxide film an electrode layer consisting of a plurality of parallel strip patterns extending in a direction substantially perpendicular to the pattern of the first oxide film; The method is characterized by comprising a step of selectively introducing impurities of the first conductivity type into the semiconductor substrate.

When the electrode layer has a two-layer structure, after forming the first electrode layer, the interlayer! ! A lamina is formed and a second xBI layer is formed in areas between the patterns of the first electrode layer. In addition, the semiconductor substrate below the second electrode layer is shaved to separate the first electrode layer and the second electrode layer.
In the case where different substrate surfaces are formed with the first electrode layer,
After forming the electrode layer, the second oxide film and the semiconductor substrate are etched in alignment with the first electrode layer, and after this etching, an interlayer oxide film and a second electrode layer are sequentially formed. When using ion implantation for programming, it may be performed using a required mask before forming each electrode layer.

(Function) In the read-only memory device of the present invention, an impurity region of a conductivity type opposite to that of the semiconductor substrate is formed under a thick insulating film, and the impurity region functions as a source/drain region of a memory transistor. The film is used for element isolation, and by utilizing the lower part as the source/drain region, the degree of integration of the read-only memory device can be greatly improved. By forming a plurality of parallel electrode layers in a substantially perpendicular direction to the pattern, a memory transistor is connected in parallel to the source/drain region.
It becomes an R-type cell. In this NOR type cell structure, each transistor is connected in parallel, so the driving ability does not decrease depending on the number of transistors. Therefore, a highly integrated read-only memory with sufficient cell driving ability The device will be obtained.

In the above method for manufacturing a read-only memory device, an oxidation-resistant film is used to obtain a thick oxide film. and,
By introducing an impurity of conductivity type opposite to that of the semiconductor substrate in a manner consistent with the oxidation-resistant film, and then growing a thick oxide film using the oxidation-resistant film, an impurity region is formed in a manner consistent with the bottom of the thick oxide film. will be done. Further, in the case where the electrode layer has a two-layer structure, when forming the second electrode layer, the first electrode layer, which is the first layer, also functions as part of a mask. Furthermore, in a manufacturing method in which the electrode layer has a two-layer structure and the region corresponding to the second electrode layer is removed by etching, impurities are introduced in a rough pattern for programming into the first electrode layer. enable.

〔Example〕

In this embodiment, a read-only memory device (ROM
) is an example.

First, the structure of the memory cell array will be explained with reference to FIG.

The memory cell array is composed of memory cells arranged in a matrix, and each memory cell is composed of one memory transistor 100.

The gate of the memory transistor 100 is connected to the word line W.
, -W, . . . are common to the memory transistors 100 arranged in the row direction. This memory transistor 1
The source/drain region 00 is common to the memory transistors 100 in each column, and linear source/drain regions S/D1 to S/D3° . . . are formed. As described later, these source/drain regions S/DI-3
/D 3. ... is 0 formed under the thick oxide film.
In the illustrated example, memory transistors 100 adjacent in the row direction have a common source/drain region 1iJf.
Among the memory transistors 100 adjacent in the row direction, source/drain regions S/D2 are common to the two memory transistors 100 and 100.

Next, the structure of the memory cell portion will be explained with reference to FIGS. '51 to 5.

FIG. 1 is a plan view of the ROM of this embodiment. In FIG. It extends in the Y direction in the figure. Source/drain regions 107 are formed in a consistent manner under this thick oxide film 102.

A first layer of polysilicon J, which is a first electrode layer, is formed in a plurality of parallel strip patterns in the X direction in the figure, which is a direction perpendicular to these thick oxide films 102.
ii103 and a second N-th polysilicon layer 104, which is a second electrode layer, are formed.

The first polysilicon layer 103 is formed in strip-like patterns parallel to each other, and adjacent patterns have a width of 1
It has an interval of 1. Second layer polysilicon layer 10
4 is formed to cover the region between the first polysilicon layers 103, and a part of each end in the Y direction is a planar mold on the end of the tm-th polysilicon layer 1ii 103. . Therefore, the memory transistors are formed in parallel with substantially no spacing in the Y direction, and the read-only memory device can have a high degree of integration.

The approximately square pattern 105 is the first layer of polysilicon 3
The substantially square pattern 106 is a window of a mask for programming by ion implantation into the lower part of the second layer polysilicon N104. Each of these 10 patterns
5 and 106 are polysilicon layers 103 in the Y direction, respectively.
, 104, and is a large opening extending over the pair of thick oxide films 102, 102 in the X direction. During ion implantation using the pattern 105, the pair of thick oxide films 102 and 102 also function as part of the mask together with the resist mask. Since the protruding portion in the Y direction is etched away by etching consistent with the first polysilicon layer 103, it is resistant to mask displacement. In addition, when performing ion implantation using the pattern 106, a pair of thick oxide 1i102,
Since the polysilicon layer 102 and the first polysilicon layer 103 function as a mask, it is resistant to mask displacement. Therefore, even if the degree of integration increases, programming can be performed reliably.

2 and 3 are cross sections taken in the X direction in the figures.

FIG. 2 is a cross section cut at the second polysilicon layer 104, and thick oxide films 102, 102 are formed on the surface of the P-type silicon substrate 101, spaced apart on the surface. On the lower surface of the silicon substrate 101, an n-type impurity region 107 is formed in a consistent manner. This n° type impurity region 107 functions as the source/drain region of the memory transistor. The surface of the substrate in the area sandwiched between the pair of thick oxide films 102 and 102 has been etched and deepened to form a groove 109.

The thick oxidation layer 111 is formed on the bottom and side surfaces of this groove 109.
A gate oxide H10B formed thinner than 102 is formed. Then, the 2Nth polysilicon layer 104 is continuous in cross section so as to extend from the gate oxide film 108 to the thick oxide 111102 and further over the gate oxide atoa of other memory transistors. is formed. This polysilicon layer 104 is formed in contact with the gate oxide film 10B in a region sandwiched between the pair of thick oxide films 102, 102.
2 and 102 are sufficiently isolated from the n° type impurity region 107. FIG. 3 is a cross section in the X direction of FIG. 1, but the cross section is taken at the 1Nth polysilicon layer 103. In the cross section of FIG. 3, as in FIG. 2, thick oxide films 102 are spaced apart from each other on the silicon substrate 101.
An n° type impurity region 107 is formed in a consistent manner under the thick oxide film 102 formed above.

This n° type impurity region 107 functions as the source/drain region of the memory transistor. However, in the region between the pair of thick oxide films 102, the silicon substrate 101 is not etched, and a gate oxide film 108 is simply formed on the main surface of the substrate. The 111th polysilicon JWI03 extends from above the gate oxide film 108 formed on the substrate soil surface to the thick oxide film 102 along the cross-sectional direction, and further extends from the gate oxide film 108 of other memory transistors. It is formed continuously all the way to the top.

Next, FIGS. 4 and 5 are cross-sections in the Y direction of FIG. 1, and FIG. 4 is a cross-sectional view taken at a thick oxidized MIO2. In this cross section, a thick oxide film 102 is formed on the surface of a p-type silicon substrate 101 along a linear n°-type impurity region 107 . This thick oxide film 10
2, the first Ji-th polysilicon layer 103
and second polysilicon layer 104 are formed alternately.

An end portion of the second polysilicon layer 104 overlaps the end portion of the first polysilicon layer 103 via an interlayer insulating film (not shown). FIG. 5 is a cross section of a portion corresponding to the channel type tc 81 region of each memory transistor. In this cross section, the second polysilicon layer 104
The surface of the silicon substrate 101 in a region corresponding to the area is etched and deepened. Then, the second layer of polysilicon Ji10
4 is a gate oxide film 108 on the deep groove 109.
formed through. First layer polysilicon layer 103
is formed on the gate oxide film 108 formed on the main surface of the substrate. The memory transistor consists of each polysilicon layer 10.
Formed every 3,104. Therefore, the height of the main surface of the substrate of the channel forming region is different between transistors that are adjacent to each other in the cross-sectional direction of FIG. As shown in FIG. 5, p-type impurities are selectively introduced into these channel forming regions to form impurity regions 110 and 111. The memory transistor in which these impurity regions 110 and 111 are formed in the channel forming region jJl does not turn on even when the word line is selected due to an increase in potential, and is an n° type that becomes a pair of source and drain regions. On the other hand, in a memory transistor in which no p-type impurity region is formed, conduction is not established between the n-type impurity regions 107 and 107, which serve as a pair of source/drain regions. sometimes conductive. This operational difference allows the programmed data to be read.

The read-only memory device of this embodiment having such a structure has p-type impurities [107
is formed under the thick oxide film 102,
High integration is possible, and the capacity of the ROM can be increased. Further, since the structure of the memory cell is a NOR type, the memory transistors are formed in parallel between a common source and a common drain. Therefore, the driving ability of the memory cell does not change depending on the number of transistors, and data can be read reliably and at high speed with sufficient driving ability. Further, in the read-only memory device of this embodiment, the electrode layer is composed of two polysilicon layers 103 and 104, and the second polysilicon layer 1104 is placed between the first polysilicon layers 103. By forming the memory transistors parallel to the regions, the memory transistors can be closely spaced along the length of the thick oxide 11102. This is advantageous for high integration, and in particular, by providing a step between the lower part of the first polysilicon layer 103 and the lower part of the second polysilicon layer 104, reliable programming is possible.

Next, an example of a method for manufacturing the read-only memory device of this embodiment will be described.

First, p-type impurity region 1 becomes the source/drain region.
A method of forming 23 in a consistent manner under the thick oxide film 124 will be described with reference to FIGS. 7a to 7c.

First, an oxidation-resistant film 121 made of a silicon nitride film is formed on a p-type silicon base Fi 120 via a band oxide film. Then, a resist layer 122 is coated on the oxidation-resistant layer 111121. Then, this resist layer 122 is selectively exposed and developed in a pattern in which a thick oxide film is to be formed. This pattern is a pattern in which openings are made in the shape of mutually parallel bands in the M region of the memory cell array. Next, the oxidation-resistant film 121 is patterned using the resist layer 122 having such a pattern, for example, by RIE method. Next, as shown in FIG. Using the chemical film 121 as a mask, n-type impurities such as arsenic ions are ion-implanted at a high concentration. Through this ion implantation, n-type impurity regions 123 are formed on the surface of the silicon substrate 120 in a mutually parallel strip pattern. be done. This n-type impurity region 123 can be formed in the same way as a channel stopper region formed under a normal field oxide film.

Next, the resist layer 122 is removed by ashing or the like, and the entire structure is oxidized. Due to this oxidation, the region where the oxidation-resistant film 121 is not formed, that is, the n-type impurity region 12
As shown in FIG. 7, a thick oxide film (LOCO3) 124 is formed on the surface of the region where LOCO3 is formed. In this way, the thick oxide film 124 is formed using the oxidation-resistant film 121 as a mask.
By forming this, a thick oxide film 124 that overlaps the n-type impurity region 123 in a consistent manner can be obtained.

Subsequently, the oxidation-resistant film 121 is removed, and the oxidation-resistant film 121 is removed.
The region where the gate oxide film 125 was formed is oxidized to form a gate oxide film 125 as shown in FIG. 7C. This gate oxide film 125 has a thickness thinner than the thick oxide film 124 described above.

Thereafter, implantation of impurities for programming, formation of electrode layers, etc. are performed.

Next, with reference to FIGS. 8a to 8c, the selective implantation of impurities in these programs and the process of forming electrode layers will be described.

First, as shown in FIG. 8a, gate oxidation II! of the silicon substrate 130 is performed. Impurity ions are selectively implanted into the lower part of 131. A required mask 132 is used for this ion implantation, and the impurity is implanted into the substrate surface through the opening 134 of the mask 132. The implanted impurity is, for example, a p-type impurity such as boron, and the mask 13
The second opening 134 can be made substantially wider than the region that becomes the channel formation region of the memory transistor.

This is because the thick oxide film functions as a part of the mask, and as will be explained next, etching removes the substrate surface in areas that protrude from the first polysilicon layer. Note that the mask 132, which does not cause any problem even if the ions are implanted, is made of, for example, a resist layer. Region 13 into which the impurity is implanted
3 is a channel type tc region of a transistor whose threshold voltage is set to a high voltage.

Next, the mask 132 is removed and a first polysilicon layer 135 is formed over the entire surface of the gate oxide film 131.

This first polysilicon layer 135 is patterned into strips in parallel patterns in a direction perpendicular to the in-plane direction of the cross-sectional view, which is the longitudinal direction of the thick oxide film. After patterning the first polysilicon layer 135, the gate oxide film 131 in the area between the first polysilicon layers 135 is removed, and the exposed silicon substrate 130 is etched from the surface. Cut groove 1 by
36 is formed in alignment with the first layer polysilicon IWI 35. During this etching, the end portions of impurity regions 133, which are formed to be wide, are etched away. By etching the end of impurity region 133, it is ensured that only the lower part of first polysilicon layer 135 is programmed.

After forming the groove 136 in alignment with the first polysilicon layer 135, as shown in FIG. 8, a mask 137 having an opening 138 for selectively implanting impurities is formed. do. This opening 138 is a window selectively formed in a region where the second polysilicon layer is to be formed, and the size of the opening 13B is actually the same as that of the second polysilicon layer 136. The lower part of the channel area is larger than the channel area. This is because the already formed first polysilicon layer 135 and the thick oxide film function as part of a mask, and by performing programming in a consistent manner in this way, high integration is achieved. It is possible to write sufficient data even if the and,
Using this mask 137, a p-type impurity such as boron is ion-implanted, and the impurity is selectively implanted into the region covering the groove 136.
Similarly to the region 133, the region 9 is also used as a channel forming region of a transistor with a high threshold voltage.

Next, the mask 137 is removed, and an interlayer oxide film and a gate oxide film 140 are formed by thermal oxidation or the like.

The interlayer oxide film covers the surface of the first polysilicon layer 135. Additionally, the gate oxidation 8140 is added to the trench 136.
It is formed by oxidizing the side walls and bottom surface of. After forming the interlayer oxide film and the gate oxide layer 140 in this manner, a second polysilicon layer 141 is formed on the entire surface by, for example, the CVD method. This second polysilicon layer 141 is
The groove 136 is formed along the side wall and bottom surface. After forming the second polysilicon layer 141 over the entire surface in this manner, the second polysilicon layer 141 is patterned. The patterning is performed so that the second polysilicon layer 141 is formed into a mutually parallel strip pattern, and the second polysilicon layer 141 is formed between the first polysilicon layers 135. Groove 136 formed in
The pattern is such that a part of the end portion in the cross-sectional direction overlaps the end portion of the first polysilicon layer 135 with an interlayer oxide film interposed therebetween. Second layer polysilicon layer 141
After forming, a silicon oxide film (for example, PSG) 142 is further formed as an interlayer insulating film, and an aluminum-based wiring 1143 is further formed on the silicon oxide film 142.
is formed in the desired pattern. This aluminum-based wiring 71143 functions as a main bit line or main column line connected to the n-type impurity region under the thick oxide film. Thereafter, the read-only memory device is completed by forming a passivation film and the like according to the usual process.

In the above-described method for manufacturing a read-only memory device, the impurity regions 123 that become the source/drain regions are formed using a thick oxide film 1.
Since it is formed under the polysilicon layer 24, there is no effect on the source/drain region even if impurities are introduced for programming in alignment with the polysilicon layer, and two polysilicon layers are formed. Furthermore, the first polysilicon layer 13
In order to form the groove 136 in alignment with the pattern 5, the openings 134 and 138 of the mask 132 and 137 into which impurities for programming are introduced may have a wide pattern, which is resistant to misalignment of the mask. Furthermore, by arranging the first polysilicon layer 135 and the 271st polysilicon layer 141 in parallel and sufficiently close to each other with only a thin interlayer oxide film interposed therebetween, the memory cell height can be increased. Dense arrangement becomes possible.

In the above embodiment, the electrode layer is made of two polysilicon layers, but the structure is not limited to this. It may be placed almost perpendicular to the pattern.
In addition, in the above embodiment, the structure is such that the grooves are formed at the bottom of the second polysilicon layer, but if the problem of program mask alignment can be solved, it is not necessary to form the grooves. The layer is not limited to a polysilicon layer, and may be a high melting point metal silicide, a polycide structure, a high melting point metal layer, or the like.

Furthermore, the material of the isolation Ii film is not limited to an oxide film, but may also have a structure in which a nitride film or the like is combined.

〔Effect of the invention〕

In the read-only memory device and its manufacturing method of the present invention,
First, the impurity regions that become the source and drain regions are thick! Since it is formed at the bottom of the film, high integration is possible, and despite this high integration, the memory cell is of the NOR type, so the driving ability of the memory cell can be maintained.

Also, 1st. When using the second electrode layer, it is possible to increase the density in the channel width direction of the memory transistor, and at the same time, by combining etching and self-alignment, programming impurities can be reliably introduced, increasing the integration density. This is particularly advantageous when the

[Brief explanation of the drawing]

FIG. 1 is a plan view of essential parts of an example of a read-only memory device of the present invention, FIG. 2 is a sectional view taken along the line T in FIG. 1, and FIG.
Figure II! -1 [1-line sectional view, Figure 4 is IV- of Figure 1
5 is a sectional view taken along the line IV, and Figure 5 is a sectional view taken along the ■-V line in Figure 1.
The figure is a circuit diagram of the memory cell array of the above example. 7th
Figures a to 7C are process cross-sectional views for explaining a part of the manufacturing method of the above-mentioned example, and Figures 8a to 8C illustrate another part of the manufacturing method of the above-mentioned example. FIG. 3 is a cross-sectional view of each step for explanation. 101, 12 102, 12 103.13 104, 14 107, 12 108, 12 0.130...Silicon base film 4...Thick oxide film 5...First polysilicon layer...・Second layer polysilicon layer 3...Impurity region 5.131...Thin oxide film

Claims (6)

[Claims] (1) A plurality of thick first insulating films formed in parallel strip patterns on the surface of a first conductivity type semiconductor substrate, and a plurality of thick first insulating films formed on the semiconductor substrate below the first insulating films. a second insulating film formed on the surface of the semiconductor substrate between the second conductivity type impurity region and the first insulating film and having a thickness thinner than the first insulating film; an electrode layer formed on the insulating film in a plurality of strip-shaped patterns extending in a direction substantially perpendicular to the pattern of the first insulating film and parallel to each other, the semiconductor below the electrode layer; A read-only memory device characterized in that it is programmed by selectively introducing impurities into the surface of a substrate. (2) a first electrode layer in which the electrode layer extends on the second insulating film in a direction substantially perpendicular to the pattern of the first insulating film and is formed in a plurality of mutually parallel strip-shaped patterns; 2nd above
a second electrode layer formed in a plurality of strip-shaped patterns parallel to the first electrode layer in a region between the first electrode layers on the insulating film; An interlayer insulating film is formed between the first electrode layer and the second electrode layer, and programming is performed by selectively introducing impurities into the surface of the semiconductor substrate below the first electrode layer and the second electrode layer. The read-only memory device according to claim 1, characterized in that: (3) The read-only memory device according to claim 2, wherein the surface of the semiconductor substrate under the second electrode layer is deeper than the surface of the semiconductor substrate under the first electrode layer. (4) forming an oxidation-resistant film having a strip pattern parallel to each other on the surface of the semiconductor substrate of the first conductivity type; and forming an impurity of the second conductivity type on the surface of the semiconductor substrate in a manner consistent with the oxidation-resistant film; oxidizing the surface of the semiconductor substrate using the oxidation-resistant film as a mask to form a thick first oxide film; and removing the oxidation-resistant film from the semiconductor substrate. and forming a second oxide film thinner than the first oxide film in a region other than the first oxide film of the semiconductor substrate, and forming the first oxide film on the second oxide film. forming an electrode layer consisting of a plurality of parallel strip patterns extending in a direction substantially perpendicular to the oxide film pattern; and selectively applying impurities of a first conductivity type to the semiconductor substrate below the electrode layer. 1. A method of manufacturing a read-only memory device, comprising the step of: (5) forming an oxidation-resistant film having a parallel strip pattern on the surface of the semiconductor substrate of the first conductivity type; and adding an impurity of the second conductivity type to the surface of the semiconductor substrate in a manner consistent with the oxidation-resistant film. oxidizing the surface of the semiconductor substrate using the oxidation-resistant film as a mask to form a thick first oxide film; and removing the oxidation-resistant film from the semiconductor substrate. and forming a second oxide film thinner than the first oxide film in a region other than the first oxide film of the semiconductor substrate, and forming the first oxide film on the second oxide film. forming a first electrode layer consisting of a plurality of parallel strip patterns extending in a direction substantially perpendicular to the oxide film pattern; and forming an interlayer insulating film covering each of the first electrode layers. and forming the first oxide film on the second oxide film between the first electrode layer.
forming second electrode layers each having a band-like pattern parallel to the electrode layer; and doping impurities of a first conductivity type on the semiconductor substrate below the first electrode layer and the second electrode layer. 1. A method for manufacturing a read-only memory device, comprising the step of selectively introducing the memory device. (6) forming an oxidation-resistant film having a parallel band pattern on the surface of the semiconductor substrate of the first conductivity type, and adding impurities of the second conductivity type to the surface of the semiconductor substrate in a manner consistent with the oxidation-resistant film; oxidizing the surface of the semiconductor substrate using the oxidation-resistant film as a mask to form a thick first oxide film; and removing the oxidation-resistant film from the semiconductor substrate. and forming a second oxide film thinner than the first oxide film in a region other than the first oxide film of the semiconductor substrate, and the semiconductor substrate on which the first electrode layer is to be formed. selectively introducing impurities of a first conductivity type into the surface of the second oxide film; a step of etching the second oxide film and the semiconductor substrate in alignment with the first electrode layer; and a step of etching the second oxide film and the semiconductor substrate in a manner consistent with the first electrode layer; a step of introducing an impurity of a first conductivity type, and a step parallel to the first electrode layer with a second oxide film interposed between the surface of the etched semiconductor substrate and the first electrode layer, respectively; A method for manufacturing a read-only memory device, comprising the step of forming second electrode layers each having a strip-like pattern.