JPH0317246B2 - - Google Patents
Info
- Publication number
- JPH0317246B2 JPH0317246B2 JP59057916A JP5791684A JPH0317246B2 JP H0317246 B2 JPH0317246 B2 JP H0317246B2 JP 59057916 A JP59057916 A JP 59057916A JP 5791684 A JP5791684 A JP 5791684A JP H0317246 B2 JPH0317246 B2 JP H0317246B2
- Authority
- JP
- Japan
- Prior art keywords
- transistor
- collector
- base
- capacitor
- whose
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/26—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback
- H03K3/28—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback
- H03K3/281—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback using at least two transistors so coupled that the input of one is derived from the output of another, e.g. multivibrator
- H03K3/286—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback using at least two transistors so coupled that the input of one is derived from the output of another, e.g. multivibrator bistable
- H03K3/288—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback using at least two transistors so coupled that the input of one is derived from the output of another, e.g. multivibrator bistable using additional transistors in the input circuit
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
- H03K3/037—Bistable circuits
- H03K3/0375—Bistable circuits provided with means for increasing reliability; for protection; for ensuring a predetermined initial state when the supply voltage has been applied; for storing the actual state when the supply voltage fails
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
Description
【発明の詳細な説明】
(技術分野)
本発明は、雑音の発生し易い場所で使われる使
われるフリツプフロツプ回路に関する。DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a flip-flop circuit used in a place where noise is likely to occur.
(従来技術)
従来、フリツプフロツプ回路は、第1図に示す
ような回路構成をしており、接地ライン1と電源
ライン2間に負荷抵抗12,13と4つのトラン
ジスタ6〜9とが接続されている。トランジスタ
6はトランジスタ7と並列に接続され、そのベー
スにセツト信号入力端子3が接続されている。ト
ランジスタ7のベースは抵抗11を介して出力端
子5に接続されている。出力端子と接地ライン1
間にはトランジスタ8と9とが並列に接続されて
おり、トランジスタ8のベースは抵抗10を介し
てトランジスタ6と7のコレクタに接続されてい
る。トランジスタ9のベースにはリセツト信号入
力端子4が接続されている。ここで各トランジス
タのベース電圧は第2図に示すようである。電源
ライン2と接地ライン1間の電位差が安定な場合
には、このフリツプフロツプ回路の動作に問題は
ないが、自動車電装品のような場合、点火火花の
ノイズ等により、電源ライン2の電位が接地ライ
ン1の電位付近まで下がり、トランジスタ6〜9
をカツトオフしてしまうことがある。この場合、
電源ライン2が元のレベルに復帰しても、トラン
ジスタ6のベース、又はトランジスタ9のベース
にセツト信号、あるいはリセツト信号が入らない
場合には、トランジスタ7か8のどちらが先に導
通状態になるかわからないため、フリツプフロツ
プ回路の出力5は一意的に決まらず誤動作を起こ
してしまう。(Prior Art) Conventionally, a flip-flop circuit has a circuit configuration as shown in FIG. 1, in which load resistors 12 and 13 and four transistors 6 to 9 are connected between a ground line 1 and a power supply line 2. There is. Transistor 6 is connected in parallel with transistor 7, and has its base connected to set signal input terminal 3. The base of transistor 7 is connected to output terminal 5 via resistor 11. Output terminal and ground line 1
Transistors 8 and 9 are connected in parallel between them, and the base of transistor 8 is connected to the collectors of transistors 6 and 7 via a resistor 10. A reset signal input terminal 4 is connected to the base of the transistor 9. Here, the base voltage of each transistor is as shown in FIG. If the potential difference between power line 2 and ground line 1 is stable, there will be no problem with the operation of this flip-flop circuit, but in cases such as automotive electrical components, the potential of power line 2 may become grounded due to noise from ignition sparks, etc. The voltage drops to near the potential of line 1, and transistors 6 to 9
may be cut off. in this case,
Even if power supply line 2 returns to its original level, if the set signal or reset signal does not enter the base of transistor 6 or the base of transistor 9, which of transistors 7 or 8 becomes conductive first? Since this is not known, the output 5 of the flip-flop circuit is not uniquely determined, resulting in malfunction.
(発明の目的)
本発明の目的は、ノイズの発生しやすい場所で
使用されるIC回路等に使用される対ノイズ性に
優れたフリツプフロツプ回路を提供することにあ
る。(Object of the Invention) An object of the present invention is to provide a flip-flop circuit with excellent noise resistance for use in IC circuits and the like used in places where noise is likely to occur.
(本発明の構成、作用、効果)
本発明によれば、コレクタがそれぞれの負荷に
接続された第1および第2のトランジスタと、第
1のトランジスタのベースを第2のトランジスタ
のコレクタに接続する第1の抵抗と、第2のトラ
ンジスタのベースを第1のトランジスタのコレク
タに接続する第2の抵抗と、第1の抵抗に並列に
接続される第1の容量素子と、第1のトランジス
タのコレクタと基準電位間に接続される第2の容
量素子と、第2のトランジスタのコレクタ出力を
ベースに受けエミツタが電流源を介して電源端子
に接続された第3のトランジスタと、第1のトラ
ンジスタのコレクタ出力をベースに受けエミツタ
が前述の電流源を介して電源端子に接続されて第
3のトランジスタとともに差動増幅器を構成する
第4のトランジスタと、コレクタ・エミツタ間が
第2の容量素子に並列に接続されベースに第4の
トランジスタのコレクタ出力を受ける第5のトラ
ンジスタとを含むフリツプ・フロツプ回路を得
る。(Configuration, operation, and effects of the present invention) According to the present invention, the first and second transistors have collectors connected to respective loads, and the base of the first transistor is connected to the collector of the second transistor. a first resistor, a second resistor connecting the base of the second transistor to the collector of the first transistor, a first capacitive element connected in parallel to the first resistor, and a second resistor connecting the base of the second transistor to the collector of the first transistor; a second capacitive element connected between the collector and a reference potential, a third transistor whose base receives the collector output of the second transistor and whose emitter is connected to a power supply terminal via a current source, and a first transistor. A fourth transistor receives the collector output from the base and whose emitter is connected to the power supply terminal via the above-mentioned current source to form a differential amplifier together with the third transistor, and a second capacitive element is connected between the collector and emitter. A flip-flop circuit is obtained which includes a fifth transistor connected in parallel and whose base receives the collector output of the fourth transistor.
本発明のフリツプフロツプ回路では第1の容量
素子は、セツト状態において、電源が接地電位に
まで落ちて各トランジスタがカツトオフしても、
電源が回復した時にスピードアツプコンデンサと
して働き第1のトランジスタを導通させる。又、
第2の容量素子は、リセツト状態において電源が
振れて、各トランジスタがカツトオフしても、こ
のコンデンサには電荷が充電されており第2のト
ランジスタを導通させるように働く。このように
2つの容量素子により、電源ラインの不安定性か
らくるフリツプフロツプ回路の誤動作を防止する
ことができる。 In the flip-flop circuit of the present invention, the first capacitive element, in the set state, can be used even if the power supply drops to ground potential and each transistor is cut off.
When power is restored, it acts as a speed-up capacitor and makes the first transistor conductive. or,
The second capacitive element acts to make the second transistor conductive because the capacitor is charged with electric charge even if the power supply fluctuates in the reset state and each transistor is cut off. In this way, the two capacitive elements can prevent the flip-flop circuit from malfunctioning due to instability of the power supply line.
(発明の実施例)
次に、図面を参照して、本発明をより詳細に説
明する。(Embodiments of the Invention) Next, the present invention will be described in more detail with reference to the drawings.
第3図は本発明の一実施例による回路図であ
る。トランジスタ6〜9等で構成される通常のフ
リツプフロツプにコンデンサ14,24とトラン
ジスタ16〜19等で構成される差動増幅器と、
その負荷である抵抗20,21、トランジスタ2
2,23が付加されている。通常の動作はセツト
信号入力端子3にセツト信号が入ると、トランジ
スタ6が導通状態となりトランジスタ8がカツト
オフとなる。このため、リセツト信号がリセツト
信号入力端子4に入つていなければ、トランジス
タ8,9のコレクタは、高電位となり、トランジ
スタ7を導通状態にし、セツト信号がなくなつて
トランジスタ6がカツトオフしても、トランジス
タ7が導通状態を維持し、そのコレクタ電圧は、
低い状態を維持し、トランジスタ8はカツトオフ
した状態を維持する。このため、出力端子5は高
電位に維持される。逆に、この状態でリセツト信
号入力端子4にリセツト信号が入つた場合には、
トランジスタ9が導通状態になるため、コレクタ
電圧が低電位となり、トランジスタ7がカツトオ
フする。このため、トランジスタ6,7のコレク
タ電圧は高電位となり、トランジスタ8を導通状
態にし、リセツト信号がなくなつても、出力端子
5は低電位に維持される。 FIG. 3 is a circuit diagram according to an embodiment of the present invention. A normal flip-flop consisting of transistors 6 to 9, etc., a differential amplifier consisting of capacitors 14 and 24, and transistors 16 to 19, etc.,
Resistors 20, 21 and transistor 2 which are the loads
2 and 23 are added. In normal operation, when a set signal is input to the set signal input terminal 3, the transistor 6 becomes conductive and the transistor 8 is cut off. Therefore, if the reset signal is not input to the reset signal input terminal 4, the collectors of the transistors 8 and 9 will be at a high potential, making the transistor 7 conductive, and even if the set signal disappears and the transistor 6 is cut off. , transistor 7 remains conductive, and its collector voltage is
remains low, and transistor 8 remains cut off. Therefore, the output terminal 5 is maintained at a high potential. Conversely, if a reset signal is input to reset signal input terminal 4 in this state,
Since transistor 9 becomes conductive, the collector voltage becomes a low potential and transistor 7 is cut off. Therefore, the collector voltages of transistors 6 and 7 become high potential, making transistor 8 conductive, and output terminal 5 is maintained at low potential even if the reset signal is no longer present.
この回路で、雑音が入り、電源ライン2が不安
定となり、各トランジスタがカツトオフするよう
な状態が起こる場合、まず、セツト信号が入つた
状態で出力が高電位の場合には、各トランジスタ
がカツトオフする前の状態で、トランジスタ16
〜19で構成されるコンパレータのトランジスタ
17,19が導通状態にあり、コンデンサ24は
放電され、ほとんど電荷がたまつていない。この
状態で電源電圧が復帰する時には、コンデンサ2
4より先にスピードアツプコンデンサ14が充電
され、トランジスタ8,9のコレクタ電圧を高電
位にし、トランジスタ7を導通状態にし、出力を
高電位に保つようになる。逆にリセツト信号が入
つていた場合には、コンデンサ24が高電位に充
電されているため、各トランジスタがカツトオフ
しても、充電された電荷がベース抵抗10を通つ
て、トランジスタ8のベースに流れ、トランジス
タ8を導通状態にし出力を低電位に保つようにな
る。第4図は、コンパレータのトランジスタを2
個で構成した例である。 In this circuit, if a situation occurs in which noise enters, power line 2 becomes unstable, and each transistor is cut off, first, if the set signal is input and the output is at a high potential, each transistor will be cut off. Transistor 16 in the state before
The transistors 17 and 19 of the comparator made up of transistors 17 and 19 are in a conductive state, and the capacitor 24 is discharged and has almost no charge accumulated therein. When the power supply voltage is restored in this state, capacitor 2
4, the speed-up capacitor 14 is charged, the collector voltages of the transistors 8 and 9 are brought to a high potential, the transistor 7 is made conductive, and the output is kept at a high potential. Conversely, when the reset signal is input, the capacitor 24 is charged to a high potential, so even if each transistor is cut off, the charged charge passes through the base resistor 10 and flows to the base of the transistor 8. The current flows, making the transistor 8 conductive and keeping the output at a low potential. Figure 4 shows two transistors in the comparator.
This is an example of a configuration consisting of
このように、本発明のフリツプフロツプ回路に
より、自動車電装品のような雑音の多発する場所
に使つた場合にも誤動作を防止することができ
る。又、記憶保持のためにはセツト側とリセツト
側の両方に容量の大きなコンデンサをつけるのが
一般的であるが、本発明の回路では、容量の大き
なコンデンサはコンデンサ24の1つでよくモノ
リシツクICで回路を構成する場合、1方のコン
デンサ14は、IC内部に作ることができるため、
外付け部品を減らし、信頼性を高めることができ
た。 As described above, the flip-flop circuit of the present invention can prevent malfunctions even when used in a place where there is a lot of noise, such as in automobile electrical equipment. Furthermore, in order to maintain memory, it is common to attach large capacitance capacitors to both the set side and the reset side, but in the circuit of the present invention, the large capacitance capacitor can be one of the capacitors 24 and can be integrated into a monolithic IC. When configuring a circuit, one capacitor 14 can be made inside the IC, so
We were able to reduce the number of external parts and increase reliability.
第1図は、従来のフリツプフロツプ回路の回路
図、第2図はその各部の電圧波形図、第3図は本
発明の一実施例によるフリツプフロツプ回路の回
路図、第4図は本発明の他の実施例によるフリツ
プフロツプ回路の回路図である。
トランジスタ……6〜9,16〜19,22,
23、抵抗……10〜13,15,20,21、
コンデンサ……14,24、接地ライン……1、
電源ライン……2。
FIG. 1 is a circuit diagram of a conventional flip-flop circuit, FIG. 2 is a voltage waveform diagram of each part thereof, FIG. 3 is a circuit diagram of a flip-flop circuit according to an embodiment of the present invention, and FIG. 4 is a circuit diagram of a flip-flop circuit according to another embodiment of the present invention. FIG. 3 is a circuit diagram of a flip-flop circuit according to an embodiment. Transistor...6-9, 16-19, 22,
23, Resistance...10~13,15,20,21,
Capacitor...14, 24, Ground line...1,
Power line...2.
Claims (1)
ンに接続された第1および第2のトランジスタ
と、該第1のトランジスタのベースと前記第2の
トランジスタのコレクタとの間に接続された第1
の抵抗と第1の容量との並列回路と、前記第2の
トランジスタのベースと前記第1のトランジスタ
のコレクタとの間に接続された第2の抵抗と、前
記第1のトランジスタのコレクタと基準電位との
間に接続された第2の容量と、ベースが前記第2
のトランジスタのコレクタに接続され、エミツタ
が電流源を介して前記電源ラインに接続された第
3のトランジスタと、ベースが前記第1のトラン
ジスタのコレクタに接続され、エミツタが前記第
3のトランジスタのエミツタに接続されて前記第
3のトランジスタとともに差動回路を構成する第
4のトランジスタと、エミツタ・コレクタ通路が
前記第2の容量に並列に接続され、ベースに前記
第4のトランジスタのコレクタ出力を受ける第5
のトランジスタとを含むことを特徴とするフリツ
プフロツプ回路。1 first and second transistors whose collectors are connected to a power supply line via their respective loads; and a first transistor whose collectors are connected between the base of the first transistor and the collector of the second transistor.
a parallel circuit of a resistor and a first capacitor; a second resistor connected between the base of the second transistor and the collector of the first transistor; the collector of the first transistor and a reference; a second capacitor connected between the potential and the base connected to the second capacitor;
a third transistor whose base is connected to the collector of the first transistor and whose emitter is connected to the power supply line via a current source; and whose base is connected to the collector of the first transistor and whose emitter is connected to the emitter of the third transistor. a fourth transistor connected to the second capacitor to form a differential circuit together with the third transistor, an emitter-collector path connected in parallel to the second capacitor, and a base receiving the collector output of the fourth transistor. Fifth
A flip-flop circuit comprising a transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59057916A JPS60201718A (en) | 1984-03-26 | 1984-03-26 | Flip-flop circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59057916A JPS60201718A (en) | 1984-03-26 | 1984-03-26 | Flip-flop circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60201718A JPS60201718A (en) | 1985-10-12 |
| JPH0317246B2 true JPH0317246B2 (en) | 1991-03-07 |
Family
ID=13069317
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59057916A Granted JPS60201718A (en) | 1984-03-26 | 1984-03-26 | Flip-flop circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60201718A (en) |
-
1984
- 1984-03-26 JP JP59057916A patent/JPS60201718A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS60201718A (en) | 1985-10-12 |
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